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14 - bit, 170 msps/250 msps, jesd204b, analog - to - digital converter data sheet ad9683 rev. 0 document feedback information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademark s and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 ? 2013 analog devices, inc. all rights reserved. technical support www.analog.com f eatures jesd204b subclass 0 or subclass 1 coded serial digital outputs signal - to - noise ratio ( snr ) = 7 0. 6 dbfs at 185 mhz a in and 250 msps spurious - free dynamic range ( sfdr ) = 88 dbc at 185 mhz a in and 250 msps total power con sumption: 43 4 mw at 250 msps 1.8 v supply voltages integer 1 - to -8 input clock d ivider sample rates of up to 2 50 msps if sampling frequencies of up to 40 0 mhz internal analog - to - digital converter ( adc ) voltage reference flexible analog input range 1 .4 v p - p to 2 .0 v p - p (1.75 v p - p no minal ) adc clock duty cycle stabilizer (dcs) serial port control energy saving power - down modes applications communications diversity radio systems multimode digital receivers (3g) td - scdma, wim ax , w - cdma, cdma2000, gsm, edge, lte docsis 3.0 cmts upstre am receive paths hfc digital reverse path receivers smart antenna systems electronic test and measurement equipment r adar r eceivers comsec radio architectures ied detection/jamming systems general - purpose software radios broadband data applications ultraso und e quipment functional block dia gram cml, tx outputs jesd204b interface high speed serializers pipeline 14-bit adc cmos digital input cmos digital output fast detect control registers clock generation avdd sdio sclk fd pdwn serdout0 cs drvdd dvdd agnd dgnd drgnd cmos digital input/output ad9683 rst vin+ vin? vcm sysref syncinb clk rfclk 1 1410-001 figure 1. general description the ad9683 is a 14 - bit adc with sampling speeds of up to 250 msps. the ad9683 is designed to support communications applications where low cost, small size, wide bandwidth, and versatility are desired. the adc core features a multistage, differential pipelined architecture with integrated output error correction logic. the adc core features wide bandwidth inputs supporting a variety of user - selectable input ranges. an integrated voltage reference eases design considerations. a duty cycle stabilizer (dcs) is provided to compensate for variations i n the adc clock duty cycle , allowing the converter to maintain excellent performance. the jesd204b high speed serial interface reduces board routing requirements and lowers pin count requirements for the receiving device. the adc output data is routed dire ctly to the jesd204b serial output lane. these outputs are at cml voltage levels. data can be sent through the lane at the maximum sampling rate of 250 msps, which results in a lane rate of 5 gbps. synchronization inputs (syncinb and sysref) are provided .
ad9683 data sheet rev. 0 | page 2 of 44 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 functional block diagram .............................................................. 1 general description ......................................................................... 1 revision history ............................................................................... 2 product highlights ........................................................................... 3 specifications ..................................................................................... 4 adc dc specifications ............................................................... 4 adc ac specifications ............................................................... 5 digital specifications ................................................................... 6 switching specifications .............................................................. 8 timing specifications .................................................................. 9 absolute maximum ratings .......................................................... 10 thermal characteristics ............................................................ 10 esd caution ................................................................................ 10 pin configuration and function descriptio ns ........................... 11 typical performance characteristics ........................................... 13 equivalent circuits ......................................................................... 18 theory of operation ...................................................................... 19 adc architecture ...................................................................... 19 analog input considerations .................................................... 19 voltage reference ....................................................................... 20 clock input considerations ...................................................... 21 power dissipation and stand by mode ..................................... 23 digital outputs ............................................................................... 24 jesd204b transmit top level description ............................ 24 adc overrange and gain control .......................................... 29 dc correction (dcc) ................................................................... 31 dc correction bandwidth ........................................................ 31 dc correction readback .......................................................... 31 dc correction freeze ................................................................ 31 dc correction enable bits ....................................................... 31 serial port interface (spi) .............................................................. 32 configuration using the spi ..................................................... 32 hardware interface ..................................................................... 32 spi accessible features .............................................................. 33 memory map .................................................................................. 34 reading the memory map register table ............................... 34 memory map register table ..................................................... 35 memory map register descriptions ........................................ 38 applications informatio n .............................................................. 43 design guidelines ...................................................................... 43 outline dimensions ....................................................................... 44 ordering guide .......................................................................... 44 r evis ion h istory 4 /13 revision 0 : initial versi on
data sheet ad9683 rev. 0 | page 3 of 44 flexible power - down options allow significant power savings, when desired. programmable overrange level detection is supported via the dedicated fast detect pins. programming for setup and control is accomplished using a 3 - wire spi - compatible serial interface. the ad9683 is available in a 32 - lead lfcsp and is specified over the industrial temperature range of ?40c to +85c. this product is protected by a u.s. patent. product highlights 1. integrated 14 - bit, 170 msps/ 250 msps adc. 2. the configurable jesd204b output block supports lane rates up to 5 gbps. 3. an on - chip , phase - locked loop ( pll) allows u sers to provide a single adc sampling clock; the pll multiplies the adc sampling clock to produce the corresponding jesd204b data rate clock . 4. support for an optional rf c lock input to ease system board design. 5. proprietary differential input maintains excel lent snr performance for input frequencies of up to 4 0 0 mhz. 6. operation from a single 1.8 v power supply. 7. standard serial port interface (spi) that supports various product features and functions , such as controlling the clock dcs , power - down, test modes, v oltage reference mode, overrange fast detection, and serial output configuration.
ad9683 data sheet rev. 0 | page 4 of 44 specifications adc dc specification s avdd = 1.8 v, drvdd = 1.8 v, dvdd = 1.8 v, maximum sample rate for speed grade , vin = ?1.0 dbfs differential input, 1.75 v p - p full - scale input range , duty cycle stabilizer enabled, default spi , unless otherwise noted. table 1 . ad9683 - 170 ad9683 - 250 parameter temperature min typ max min typ max unit resolution full 14 14 bits accuracy no missing codes full guaranteed guaranteed offset error full 9 9 mv gain error full ?6 .6/ ?0.3 ?5.3/ +1.2 %fsr differential nonlinearity (dnl) full 0.8 0.75 lsb 25c 0. 5 0. 5 lsb integral nonlinearity (inl) 1 full 1.6 2.7 lsb 25c 0.8 1.5 lsb temperature drift offset error full 7 7 ppm/c gain er ror full 1 3 39 ppm/c input referred noise vref = 1. 75 v 25c 1. 38 1.4 2 lsb rms analog input input span full 1.75 1.75 v p -p input capacitance 2 full 2.5 2.5 pf input resistance 3 full 20 20 k? input common - mode v oltage full 0.9 0.9 v power supplies supply voltage avdd full 1.7 1.8 1.9 1.7 1.8 1.9 v drvdd full 1.7 1.8 1.9 1.7 1.8 1.9 v dvdd full 1.7 1.8 1.9 1.7 1.8 1.9 v supply current i avdd full 135 151 1 49 163 ma i drvdd + i dv dd full 68 73 92 97 ma power consumption sine wave input full 3 6 5 403 43 4 468 mw standby power 4 full 221 266 mw power - down power 5 full 9 9 mw 1 measured with a low input frequency, full - scale sine wave. 2 input capacitance refers to the effective capacitance between one differential input pin and i ts complement. 3 input resistance refers to the effective resistance between one differential input pin and its complement. 4 standby power is measured with a low input frequency, full - scale sine wave, and the clk pin s active. address 0x08 is set to 0x2 0, and the pdwn pin is asserted. 5 power - down power is measured with a low input frequency, a full - scale sine wave, rfclk pulled high, and the clk pin s active. address 0x08 is set to 0x00, and the pdwn pin is asserted.
data sheet ad9683 rev. 0 | page 5 of 44 adc ac specification s avdd = 1.8 v, drvdd = 1.8 v, dvdd = 1.8 v, maximum sample rate for speed grade , vin = ? 1.0 dbfs differential input, 1.75 v p - p full - scale input range , default spi , unless otherwise noted. table 2 . ad9683 - 170 ad9683 - 250 parameter 1 temperature min typ max min typ max unit signal - to - noise - ratio (snr) f in = 30 mhz 25c 72. 3 72. 1 dbfs f in = 90 mhz 25c 7 2.0 71. 7 dbfs full 71 dbfs f in = 140 mhz 25 c 71. 3 71. 3 dbfs f in = 185 mhz 25c 70. 5 70.6 dbfs full 70. 0 dbfs f in = 220 mhz 25c 70. 0 70.0 dbfs signal - to - noise and distortion (sinad) f in = 30 mhz 25c 71.3 70. 9 dbfs f in = 90 mhz 25c 70. 8 70. 6 dbfs full 69.9 dbfs f in = 140 mhz 25c 70. 2 70. 1 dbfs f in = 185 mhz 25c 6 9. 5 69.5 dbfs full 68. 7 dbfs f in = 220 mhz 25c 6 8 . 8 68. 7 dbfs effective number of bits (enob) f in = 30 mhz 25c 11.5 11.5 bits f in = 90 mhz 25c 11. 5 11.4 bits f in = 140 mhz 25c 11. 4 11. 4 bits f in = 185 mhz 25c 11. 3 11. 3 bits f in = 220 mhz 25c 11.1 11. 1 bits spurious - free dynamic range (sfdr) f in = 30 mhz 25c 9 4 8 7 dbc f in = 90 mhz 25c 89 8 6 dbc full 81 dbc f in = 140 mhz 25c 94 8 7 dbc f in = 185 mhz 25c 8 9 8 8 dbc full 80 dbc f in = 220 mhz 25c 8 7 8 6 dbc worst second or third harmonic f in = 30 mhz 25c ? 9 4 ? 8 7 dbc f in = 90 mhz 25c ? 89 ?8 6 dbc full ?81 dbc f in = 140 mhz 25c ?9 4 ?8 7 dbc f in = 185 mhz 25c ?8 9 ?8 8 dbc full ?80 dbc f in = 220 mhz 25c ?8 7 ?8 6 dbc worst other (harmonic or spur) f in = 30 mhz 25c ?9 9 ?9 5 dbc f in = 90 mhz 25c ?9 2 ? 9 4 dbc full ?83 dbc f in = 140 mhz 25c ?9 6 ?9 4 dbc f in = 185 mhz 25c ?9 4 ? 93 dbc full ?82 dbc f in = 220 mhz 25c ?9 5 ?9 2 dbc
ad9683 data sheet rev. 0 | page 6 of 44 ad9683 - 170 ad9683 - 250 parameter 1 temperature min typ max min typ max unit two - tone sfdr f in 1 = 184.12 mhz (?7 dbfs), f in2 = 187.12 mhz (?7 dbfs) 25c 87 87 dbc full power band width 2 25c 1000 1000 mhz 1 see the an - 835 application note , understanding high speed adc testing and evaluation for a complete set of definitions. 2 full power b andwidth is the bandwidth of operation determined by where the spectral power of the fundamental frequency is reduced by 3 db. digital specificatio ns avdd = 1.8 v, drvdd = 1.8 v, dvdd = 1.8 v, maximum sample rate for speed grade , vin = ?1.0 dbfs differential input, 1.75 v p - p full - scale input range , dcs enabled, default spi , unless otherwise noted. table 3 . parameter temp erature min typ max unit differential clock inputs (clk+, clk?) input clk clock rate full 40 6 25 mhz logic compliance cmos/lvds/lvpecl internal common - mode bias full 0.9 v differential input voltage ful l 0.3 3. 6 v p - p input voltage range full a gnd avdd v input common - mode range full 0.9 1.4 v high level input current full 0 + 60 a low level input current full ? 60 0 a input capacitance full 4 pf input resistance full 8 10 12 k? rf clock input (rfclk) rf clock rate full 625 1500 mhz logic compliance cmos/lvds/lvpecl internal bias full 0.9 v input voltage range full agnd avdd v high input voltage level full 1.2 avdd v low input voltage level full agnd 0.6 v high level input current full 0 + 150 a low level input current full ?150 0 a input capacitance full 1 pf input resistance (ac - c oupled) full 8 10 12 k? sync in input s ( sync in b +/sync in b ?) logic compliance cmos/ lvds internal common - mode bias full 0.9 v differential input voltage range full 0.3 3.6 v p - p i nput voltage range full d gnd d vdd v input common - mode range full 0.9 1.4 v high level input current full ?5 +5 a low level input current full ? 10 + 10 a input capacitance full 1 pf input resistance full 12 16 20 k?
data sheet ad9683 rev. 0 | page 7 of 44 parameter temp erature min typ max unit sysref input s (sysref +/ sysref? ) logic compliance lvds internal common - mode bias full 0.9 v differential input voltage range full 0.3 3.6 v p - p input voltage range full agnd avdd v input common - mode range full 0.9 1.4 v high level input current full ? 5 +5 a low level input current full ? 10 + 10 a input capacitance full 4 pf input resistance full 8 10 12 k? logic input ( rst ) 1 high level input voltage full 1.22 2.1 v low level input voltage full 0 0.6 v high level input curr ent full ?5 +5 a low level input current full ?10 0 ?45 a input resistance full 26 k? input capacitance full 2 pf logic input s (sclk, pdwn , cs 2 ) 3 high level input voltage full 1.22 2.1 v low level input voltage full 0 0.6 v high level input current full 45 10 0 a low level input current full ? 10 + 10 a input resistance full 26 k? input capacitance full 2 pf logic input (sdio) 3 high level input voltage fu ll 1.22 2.1 v low level input voltage full 0 0.6 v high level input current full 45 100 a low level input current full ? 10 + 10 a input resistance full 26 k? input capacitance full 5 pf digital outputs ( serdout0 +/serdout0?) logic compl iance cml differential output voltage (v od ) full 400 600 750 mv output offset voltage (v os ) full 0.75 drvdd/2 1.05 v digital outputs (s dio / fd 4 ) high level output voltage (v oh ) i oh = 50 a full 1.79 v i oh = 0.5 ma full 1.75 v i oh = 2.0 ma full 1.6 v low level output voltage (v ol ) i ol = 2.0 ma full 0.25 v i ol = 1.6 ma full 0.2 v i ol = 50 a full 0.05 v 1 pull - up. 2 needs an external pull - up. 3 pull - down. 4 compatible with jedec standard jesd8 - 7a.
ad9683 data sheet rev. 0 | page 8 of 44 switching specificat ions table 4 . ad9683 - 170 ad9683 - 250 parameter symbol temp erature min typ max min typ max unit clock input parameters conversion rate 1 f s full 40 170 40 250 msps sysref setup time to r ising edge clk 2 t refs full 300 300 ps sysref hold time from rising edge clk 2 t refh full 40 40 ps sysref setup time to rising edge rfclk 2 t refsrf full 400 400 ps sysref hold time from rising edge rfclk 2 t refhrf full 0 0 ps clk pulse width high t ch divide -by - 1 mode, dcs enabled full 2.61 2.9 3.19 1.8 2.0 2.2 ns divide -by - 1 mode, dcs disabled full 2.76 2.9 3.05 1.9 2.0 2.1 ns divide -by - 2 mode through divide -by - 8 mode full 0.8 0.8 ns aperture delay t a full 1.0 1.0 ns aperture uncertainty (jitter) t j full 0.16 0.16 ps rms data output parameters data outpu t period or unit interval (ui) full 20 f s 20 f s seconds data output duty cycle 25c 50 50 % data valid time 25c 0.8 2 0.78 ui pll lock time t lock 25c 25 25 s wake - up time standby 25c 10 10 s adc (power - down) 3 25c 250 250 s output (power - down) 4 25c 50 50 s syncinb falling edge to first k.28 characters full 4 4 multiframes cgs phase k.28 characters duration full 1 1 multiframe pipeline delay jesd204b (latency) full 36 36 c ycles 5 fast detect (latency) full 7 7 cycles 5 lane rate full 3.4 5 5 gbps uncorrelated bounded high probability (ubhp) jitter full 10 12 ps random jitter at 3.4 gbps full 2. 4 ps rms at 5 gbps full 1.7 ps rms output rise/fall time full 60 60 ps differential termination resistance 25c 100 100 ? out - of - range recovery time full 3 3 cycles 5 1 conversion rate is the clock rate after the divider. 2 refer to figure 3 for timin g diagram. 3 wake - up time adc is defined as the time required for the adc to return to normal operation from power - down mode. 4 wake - up time output is defined as the time required for jesd204b output to return to normal operation from power - down mode. 5 cy cles refers to adc conversion rate cycles.
data sheet ad9683 rev. 0 | page 9 of 44 timing specification s table 5 . parameter test conditions /comments min typ max unit spi timing requirements see figure 67 t ds set up time between the data and the rising edge of sclk 2 ns t dh hold time between the data and the rising edge of sclk 2 ns t clk period of the sclk 40 ns t s set up time between c s and sclk 2 ns t h hold time between cs and sclk 2 ns t high minimum period that sclk must be in a logic high state 10 ns t lo w minimum period that sclk must be in a logic low state 10 ns t en_sdio time required for the sdio pin to switch from an input to an output relative to the sclk falling edge (not shown in figures) 10 ns t dis_sdio time required for the sdio pin to switch from an output to an input relative to the sclk rising edge (not shown in figures) 10 ns t spi_r st time required after hard or soft reset until spi access is available (not shown in figures) 500 s timing diagrams n ? 36 n ? 35 n ? 34 n ? 33 n ? 1 n + 1 sample n analog input signal clk? clk+ clk? clk+ serdout0 sample n ? 36 encoded into 2 8b/10b symbols sample n ? 35 encoded into 2 8b/10b symbols sample n ? 34 encoded into 2 8b/10b symbols 1 1410-002 figure 2. data output timing t refs t refh t refsrf t refhrf rfclk clk? clk+ sysref+ sysref? 1 1410-003 figure 3. sysref setup and hold timing (clock in put e ither rfc lk or clk, not both)
ad9683 data sheet rev. 0 | page 10 of 44 absolute maximum rat ings table 6 . parameter rating electrical avdd to agnd ? 0.3 v to +2.0 v drvdd to drgnd ?0.3 v to +2.0 v d vdd to d gnd ?0.3 v to +2.0 v vin+, vin? to agnd ?0.3 v to avdd + 0.2 v clk+, clk? to agnd ?0.3 v to avdd + 0.2 v rfclk to agnd ?0.3 v to avdd + 0.2 v vcm to agnd ?0.3 v to avdd + 0.2 v cs , pdwn to d gnd ?0.3 v to d vdd + 0.3 v sclk to d gnd ?0.3 v to d vdd + 0.3 v sdio to d gnd ?0.3 v to d vdd + 0.3 v rst to d gnd ?0.3 v to dvdd + 0.3 v fd to d gnd ?0.3 v to dvdd + 0.3 v serdout0 +, serdout0 ? to agnd ?0.3 v to drvdd + 0.3 v syncinb+, syncinb? to dgnd ?0.3 v to dvdd + 0.3 v sys ref +, sysref ? to a gnd ?0.3 v to a vdd + 0.3 v environmen tal operating temperature range (ambient) ?40c to +85c maximum junction temperature under bias 150c storage temperature range (ambient) ? 65 c to +125c stresses above those listed under absolute maximum ratings may cause permanent damage to the d evice. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended peri ods may affect device reliability. thermal characterist ics the exposed pad must be soldered to the ground plane of the lfcsp package. this increases the reliability of the solder joints, maximizing the thermal capability of the package. table 7 . thermal resistance package type airflow velocity (m/s ec ) ja 1, 2 jc 1, 3 , 4 jb 1, 4 , 5 unit 32- lead lfcsp 5 mm 5 mm (cp - 32 - 1 2 ) 0 37.1 3.1 20.7 c/w 1.0 32.4 n/a n/a c/w 2. 5 29.1 n/a n/a c/w 1 per jedec 51 - 7, plus jedec 25 - 5 2s2p t est board. 2 per jedec jesd51 - 2 (still air) or jedec jesd51 - 6 (moving air). 3 per mil - s td - 883, method 1012.1. 4 n/a = not applicable. 5 per jedec jesd51 - 8 (still air). typical ja is specified for a 4 - layer printed circuit board ( pcb ) with a solid ground plane. as shown in table 7 , airflow increases heat dissipation, which reduces ja . in addition, metal in direct contact with the package leads from metal traces, through holes, ground, and power planes reduces the ja . esd caution
data sheet ad9683 rev. 0 | page 11 of 44 pin configuration an d function descripti ons notes 1. dnc = do not connec t . do not connect to this pin. 2. the exposed thermal pad on the bottom of the package provides the ground reference for avdd. this exposed pad must be connected to agnd for proper operation. rst 24 dnc 23 pdwn 22 cs 21 sclk 20 sdio 19 fd 18 dgnd 17 dvdd 1 2 3 4 5 6 7 8 rfclk clk? clk+ a vdd sysref+ sysref? a vdd 9 10 1 1 12 13 14 15 16 dgnd dvdd syncinb+ syncinb? drgnd d r vdd serdout0? serdout0+ 32 31 30 29 28 27 26 25 a vdd a vdd a vdd vin+ vin? a vdd a vdd vcm ad9683 t o p view (not to scale) 1 1410-004 figure 4 . pin configuration (top view ) table 8 . pin function desc riptions pin no. mnemonic type description adc power supplies 4, 7, 26, 27, 30, 31, 32 avdd supply analog power supply (1.8 v nominal). 10, 1 7 d vdd supply digital power supply (1.8 v nominal). 9, 18 dgnd ground ground reference for dvdd. 13 drgnd ground ground reference for drvdd. 14 drvdd supply jesd204b phy se rial output driver supply (1.8 v nominal). note that the drvdd power is referenced to the agnd plane. 24 dnc do not connect. epad ( agnd ) ground exposed pad. the exposed thermal pad on the bottom of the package provides the ground reference for avdd. this exposed pad must be connected to agnd for proper operation. adc analog 1 rfclk input adc rf clock input. 2 clk? input adc nyquist clock input complement. 3 clk+ input adc nyquist clock input true. 25 vcm output common - mode level bias output fo r analog inputs. decouple this pin to ground using a 0.1 f capacitor. 28 vin? input differential analog input (?). 29 vin+ input differential analog input (+). adc fast detect output 19 fd output fast detect indicator (cmos levels). digital input s 5 sysref+ input jesd204b lvds sysref input true . 6 sysref? input jesd204b lvds sysref input complement. 11 syncinb+ input jesd204b lvds sync input true . 12 syncinb? input jesd204b lvds sync input complement. data outputs 15 serdout0? output cml output data complement. 16 serdout0+ output cml output data true.
ad9683 data sheet rev. 0 | page 12 of 44 pin no. mnemonic type description device under test ( dut ) controls 8 rst input digital reset (active low). 20 sdio input/ o utput spi serial data i/o. 21 sclk input spi serial clock. 22 cs input spi chip select (active low). this pin needs an external pull - up. 23 pdwn input power - down input (active high). the operation of this pin depends on spi mode and can be configured as power - down or standby (see table 17).
data sheet ad9683 rev. 0 | page 13 of 44 typical performance characteristics avdd = 1.8 v, drvdd = 1.8 v, dvdd = 1.8 v, maximum sample rate for speed grade , vin = ?1.0 dbfs, 1 .75 v p - p differen tial input, dcs enabled, 16 k sample, t a = 25c , default spi , unless othe rwise noted. ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 0 10 20 30 40 50 60 70 80 amplitude (dbfs) frequenc y (mhz) third harmonic 170msps 90.1mhz a t ?1.0dbfs snr = 70.7db (71.7dbfs) sfdr = 89dbc second harmonic 1 1410-005 figure 5. ad9683 - 170 single - tone fft with f in = 90.1 mhz ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 0 10 20 30 40 50 60 70 80 amplitude (dbfs) frequenc y ( mhz ) third harmonic second harmonic 170msps 90.1mhz a t ?1.0dbfs snr = 71.1db (72.1dbfs) sfdr = 88dbc 1 1410-006 figure 6. ad9683 - 170 single - tone fft with f in = 90.1 mhz, rf clk = 680 mhz with d ivide by 4 ( address 0x09 = 0x21) ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 0 10 20 30 40 50 60 70 80 amplitude (dbfs) frequenc y (mhz) 170msps 185.1mhz a t ?1.0dbfs snr = 69.6db (70.6 dbfs) sfdr = 90dbc second harmonic third harmonic 1 1410-007 figure 7. ad9683 - 170 single - tone fft with f in = 185.1 mhz ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 0 10 20 30 40 50 60 70 80 amplitude (dbfs) frequenc y (mhz) 170msps 185.1mhz a t ?1dbfs snr = 70.1db (71.1dbfs) sfdr = 84dbc second harmonic third harmonic 1 1410-008 figure 8. ad9683 - 170 single - tone fft with f in = 185.1 mhz, rf clk = 680 mhz with d ivide by 4 ( address 0x09 = 0x21) ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 0 10 20 30 40 50 60 70 80 amplitude (dbfs) frequenc y (mhz) 170msps 305.1mhz a t ?1.0dbfs snr = 67.6db (68.6dbfs) sfdr = 85dbc second harmonic third harmonic 1 1410-009 figure 9. ad9683 - 170 single - tone fft with f in = 305.1 mhz 0 20 40 60 80 100 120 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 snr/sfdr (dbc and dbfs) input amplitude (dbfs) snr (dbfs) snr (dbc) sfdr (dbc) sfdr (dbfs) 1 1410-010 figure 10 . ad9683 - 170 single - tone snr/sfdr vs. input amplitude (a in ) with f in = 185.1 mhz
ad9683 data sheet rev. 0 | page 14 of 44 60 65 70 75 80 85 90 95 100 10 45 80 1 15 150 185 220 255 290 325 360 395 430 465 500 snr (dbfs)/sfdr (dbc) frequenc y (mhz) snr (dbfs) sfdr (dbc) 1 1410-0 1 1 figure 11 . ad9683 - 170 single - tone snr/sfdr vs. input frequency (f in ) 60 65 70 75 80 85 90 95 100 10 45 80 1 15 150 185 220 255 290 325 360 395 430 465 500 snr (dbfs)/sfdr (dbc) frequenc y (mhz) sfdr (dbc) snr (dbfs) 1 1410-012 figure 12 . ad 9683 - 170 single - tone snr/sfdr vs. input frequency (f in ), rfc lk = 680 mhz with d ivide by 4 ( address 0x09 = 0x21) ?120 ?100 ?80 ?60 ?40 ?20 0 ?90.0 ?78.5 ?67.0 ?55.5 ?44.0 ?32.5 ?21.0 ?9.5 sfdr/imd3 (dbc and dbfs) input amplitude (dbfs) imd3 (dbc) sfdr (dbc) sfdr (dbfs) imd3 (dbfs) 1 1410-013 figure 13 . ad9683 - 170 two - tone sfdr/imd 3 vs. input amp litude (a in ) with f in1 = 89.12 mhz, f in2 = 92.12 mhz, f s = 170 msps ?120 ?100 ?80 ?60 ?40 ?20 0 input amplitude (dbfs) ?90.0 ?81.7 ?73.4 ?65.1 ?56.8 ?48.5 ?40.2 ?31.9 ?23.6 ?15.3 ?7.0 sfdr/imd3 (dbc and dbfs) imd3 (dbc) sfdr (dbfs) imd3 (dbfs) sfdr (dbc) 1 1410-014 figure 14 . ad9683 - 170 two - tone sfdr/imd 3 vs. input amplitude (a in ) with f in1 = 184.12 mhz, f in2 = 187.12 mhz, f s = 170 msps ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 0 10 20 30 40 50 60 70 80 amplitude (dbfs) frequenc y (mhz) 170msps 89.12mhz a t ?7dbfs 92.12mhz a t ?7dbfs sfdr = 90dbc (97dbfs) 1 1410-015 figure 15 . ad9683 - 170 two - tone fft with f in1 = 89.12 mhz, f in2 = 92.12 mhz, f s = 170 msps ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 0 10 20 30 40 50 60 70 amplitude (dbfs) frequenc y (mhz) 170msps 184.12mhz a t ?7dbfs 187.12mhz a t ?7dbfs sfdr = 87dbc (94dbfs) 80 1 1410-016 figure 16 . ad9683 - 170 two - tone fft with f in1 = 184.12 mhz, f in2 = 187.12 mhz, f s = 170 msps
data sheet ad9683 rev. 0 | page 15 of 44 70 75 80 85 90 95 100 40 50 60 70 80 90 100 1 10 120 130 140 150 160 170 snr (dbfs)/sfdr (dbc) sample r a te (msps) sfdr (dbc) snr (dbfs) 1 1410-017 figure 17 . ad9683 - 170 single - tone s nr/sfdr vs. sample rate (f s ) with f in = 90.1 mhz 0 100000 200000 300000 400000 500000 600000 700000 n ? 7 n ? 5 n ? 3 n ? 1 n + 1 n + 3 n + 5 number of hits output code 2,097,152 t o t a l hits 1.375 lsb rms 1 28 638 7601 41248 138 1 13 384443 278480 100153 24088 2363 182 521038 598772 1 1410-018 figure 18 . ad9683 - 170 grounded input histogram ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 0 25 50 75 100 125 amplitude (dbfs) frequenc y (mhz) 250msps 90.1mhz a t ?1dbfs snr = 71db (72dbfs) sfdr = 89dbc third harmonic second harmonic 1 1410-019 figure 19 . ad9683 - 250 single - tone fft with f in = 90.1 mhz ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 0 25 50 75 100 125 amplitude (dbfs) frequenc y (mhz) third harmonic 250msps 90.1mhz a t ?1dbfs snr = 71db (72dbfs) sfdr = 89dbc second harmonic 1 1410-020 figure 20 . ad9683 - 250 single - tone fft with f in = 90.1 mhz, rfc lk = 1.0 ghz with d ivide by 4 ( address 0x09 = 0x21) ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 0 25 50 75 100 125 amplitude (dbfs) frequenc y (mhz) third harmonic 250msps 185.1mhz a t ?1dbfs snr = 69.5db (70.5dbfs) sfdr = 88dbc second harmonic 1 1410-021 figure 21 . ad9683 - 250 single - tone fft with f in = 185.1 mhz ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 0 25 50 75 100 125 amplitude (dbfs) frequenc y (mhz) third harmonic 250msps 185.1mhz a t ?1dbfs snr = 70db (71dbfs) sfdr = 85dbc second harmonic 1 1410-022 figure 22 . ad9683 - 250 single - tone fft with f in = 185.1 mhz, rfc lk = 1.0 ghz with d ivide by 4 ( address 0x09 = 0x21)
ad9683 data sheet rev. 0 | page 16 of 44 ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 0 25 50 75 100 125 amplitude (dbfs) frequenc y (mhz) third harmonic 250msps 305.1mhz a t ?1dbfs snr = 67.5db (68.5dbfs) sfdr = 85dbc second harmonic 1 1410-023 figure 23 . ad9683 - 250 single - tone fft with f in = 305.1 mhz 0 20 40 60 80 100 120 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 snr/sfdr (dbc and dbfs) input amplitude (dbfs) snr (dbfs) snr (dbc) sfdr (dbc) sfdr (dbfs) 1 1410-024 figure 24 . ad9683 - 250 single - tone snr/sfdr vs. input amplitude (a in ) with f in = 185.1 mhz 60 65 70 75 80 85 90 95 100 10 45 80 1 15 150 185 220 255 290 325 360 395 430 465 500 snr (dbfs)/sfdr (dbc) frequenc y (mhz) sfdr (dbc) snr (dbfs) 1 1410-025 figure 25 . ad9683 - 250 single - tone snr/sfdr vs. input frequency (f in ) 60 65 70 75 80 85 90 95 100 10 45 80 1 15 150 185 220 255 290 325 360 395 430 465 500 snr (dbfs)/sfdr (dbc) frequenc y (mhz) sfdr (dbc) snr (dbfs) 1 1410-026 figure 26 . ad9683 - 250 single - tone snr/sfdr vs. input frequency (f in ), rfc lk = 1.0 ghz with d ivide by 4 ( address 0x09 = 0x21) ?120 ?100 ?80 ?60 ?40 ?20 0 ?90.0 ?78.5 ?67.0 ?55.5 ?44.0 ?32.5 ?21.0 ?9.5 sfdr/imd3 (dbc and dbfs) input amplitude (dbfs) imd3 (dbc) sfdr (dbc) sfdr (dbfs) imd3 (dbfs) 1 1410-027 figure 27 . ad9683 - 250 two - tone sfdr/imd 3 vs. input amplitude (a in ) with f in1 = 89.12 mhz, f in2 = 92.12 mhz, f s = 250 msps ?120 ?100 ?80 ?60 ?40 ?20 0 ?90.0 ?78.5 ?67.0 ?55.5 ?44.0 ?32.5 ?21.0 ?9.5 sfdr/imd3 (dbc and dbfs) input amplitude (dbfs) sfdr (dbc) imd3 (dbc) sfdr (dbfs) imd3 (dbfs) 1 1410-028 figure 28 . ad9683 - 250 two - tone sfdr/imd 3 vs. input amplitude (a in ) with f in1 = 184.12 mhz, f in2 = 187.12 mhz, f s = 250 msps
data sheet ad9683 rev. 0 | page 17 of 44 ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 0 25 50 75 100 125 amplitude (dbfs) frequenc y (mhz) 250msps 89.12mhz a t ?7dbfs 92.12mhz a t ?7dbfs sfdr = 90dbc (97dbfs) 1 1410-029 figure 29 . ad9683 - 250 two - tone fft with f in1 = 89.12 mhz, f in2 = 92.12 mhz, f s = 250 msps ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 0 25 50 75 100 125 amplitude (dbfs) frequenc y (mhz) 250msps 184.12mhz a t ?7dbfs 187.12mhz a t ?7dbfs sfdr = 87dbc (94dbfs) 1 1410-030 figure 30 . ad9683 - 250 two - tone fft with f in1 = 184.12 mhz, f in2 = 187.12 mhz, f s = 250 msps 70 75 80 85 90 95 100 40 60 80 100 120 140 160 180 200 220 240 snr/sfdr (dbfs/dbc) sample r a te (msps) sfdr (dbc) snr (dbfs) 1 1410-031 figure 31 . ad9683 - 250 single - tone snr/sfdr vs. sample rate (f s ) with f in = 90.1 mhz 1 1410-032 4 161 2316 15633 70369 59901 7965 658 49 0 100000 200000 300000 400000 500000 600000 700000 n ? 7 n ? 5 n ? 3 n ? 1 n + 1 n + 3 n + 5 number of hits output code 2,097,152 t o t a l hits 1.419 lsb rms 261252 181231 520772 581334 395507 figure 32 . ad9683 - 250 grounded input histogram
ad9683 data sheet rev. 0 | page 18 of 44 equivalent circuits v i n a v d d 1 1410-033 figure 33 . equivalent analog input circuit 0 . 9 v 15k ? 15k ? c l k + c l k ? a v d d a v d d a v d d 1 1410-034 figure 34 . equivalent clock lnput circuit bias control 10k ? rfclk interna l clock driver 0.5pf a v d d 1 1410-035 figure 35 . equivalent rf clock lnput circuit v c m drv d d serdout0 serdout0 3m a 3m a 3m a 3m a r t e r m drv d d drv d d 1 1410-036 figure 36 . digital cml output circuit 40 0 ? 31 k ? d v d d sdio 1 1410-037 figure 37 . equivalent sdio circuit 40 0 ? 3 0k ? d v d d pdwn, sclk, cs 1 1410-038 figure 38 . equivalent pdwn, sclk , or cs input circuit 0 . 9 v 1 7 k ? 1 7 k ? syncinb+ syncinb? dv d d dv d d dv d d 1 1410-039 figure 39 . equivalent syncinb input circuit 0 . 9 v 1 7 k ? 1 7 k ? sysref+ sysref? a v d d a v d d a v d d 1 1410-040 figure 40 . equivalent sysref input circuit rst 400 ? 28k ? drv d d drv d d 1 1410-041 figure 41 . equivalent rst input circuit 40 0 vcm ? av d d 1 1410-042 figure 42 . equivalent vcm circuit
data sheet ad9683 rev. 0 | page 19 of 44 theory of operation the ad9683 has one analog input channel a nd one jesd204b output lane . the signal passes through several stages before appearing at the output port . the user can sample frequencies from dc to 4 00 mhz using appropriate low - pass or band - pass filtering at the adc inputs with little los s in adc perf ormance. operation above 400 mhz analog input is permitted but occurs at the expense of increased adc noise and distortion. a s ynchronizat i on capability is provided to allow synchronized timing between multiple devices. p rogramm ing and control of the ad9683 are accomplished using a 3 - pin , spi - compatible serial interface. adc architecture the ad9683 architecture consists of a front - end , samp le - and - hold c ircuit, followed by a pipelined switched capacitor adc. the quantized outputs from each stage are combined into a final 14 - bit result in the digital correction logic. the pipelined architecture permits the first stage to operate on a new input sample , and the remaining stages to operate on the preceding samples. sampling occurs on the rising edge of the clock. each stage of the pipeline, excluding the last, consists of a low resolution fl ash adc connected to a switched capacitor digital - to - anal og converter (dac) and an interstage residue amplifier (mdac). the mdac magnifies the difference between the reconstructed dac output and the flash input for the next stage in the pipeline. one bit of redundancy is used in each stage to facilitate digital correction of flash errors. the last stage simply consists of a flash adc. the input stage contains a differential sampling circuit that can be ac - or dc - coupled in differential or single - ended modes. the output staging block aligns the data, corrects erro rs, and passes the data to the output buffers. the output buffers are powered from a separate supply, allowing digital output noise to be separated from the analog core. analog input conside rations the analog input to the ad9683 is a differential , switchedcapacitor circuit that has been designed for optimum performance while processing a differential input signal. the clock signal alternatively switches the input between sample mode and hold mode (see the configuration shown in figure 43 ). when the input is switched into sample mode, the signal source must be capable of charging the sampling capacitors and settling within 1/2 clock cycle. a small resist or in series with each input can help reduce the peak transient current required from the output stage of the driving source. a shunt capacitor can be placed across the inputs to provide dynamic charging currents. this passive network creates a low - pass fi lter at the adc input; therefore, the precise values are dependent on the application. in intermediate frequency (if) undersampling applications, reduce the shunt capacitors. in combination with the driving source impedance, the shunt capacitors limit the input band - width. r efer to the an - 742 application note , frequency domain response of switched - capacitor adcs ; the an - 827 application note , a resonant approach to interfacing amplifiers to switched - capacitor adcs ; and the analog dialogue article, transformer - coupled front - end for wideband a/d converter s, for more information. c p ar 1 c p ar 1 c p ar 2 c p ar 2 s s s s s s c f b c f b c s c s b i a s b i a s v i n + h v i n ? 1 1410-043 figure 43 . switched capacitor input for best dynamic performance, match the source impedances driving vin+ and vin? and differentially balance the inputs. input common mode the analog inputs of t he ad9683 are not internally dc biased. in ac - coupled applications, the us er must provide this bias externally. configuring the input so that v cm = 0.5 avdd (or 0.9 v) is recommended for optimum performance . an on - board common - mode voltage reference is included in the design and is available from t he vcm pin. using the vcm out put to set the input common mode is recommended. optimum perform ance is achieved when the common - mode voltage of th e analog input is set by the vcm pin voltage (typically 0.5 avdd). d ecouple t he vcm pin to ground by using a 0.1 f capacitor, as described in the applications information section. place t his decoupling capacitor close to the pin to minimize the series resistance and inductance between the part and this capacitor. differential input configurations opt imum performance is achieved while driving the ad9683 in a differential input configuration. for baseband applications, the ad8138 , ada4937 - 1 , ada4938 - 1 , and ada493 0 - 1 differential driver s provide excellent p erformance and a flexible interface to the adc.
ad9683 data sheet rev. 0 | page 20 of 44 the output common - mode voltage of the ad a493 0 - 1 is easily set with the vcm pin of the ad9683 (see figure 44 ), and the driver can be configured in a sallen - key filter topology to provide band limiting of the input signal. v i n 76 . 8 ? 120 ? 0 . 1 f 200 ? 200 ? 90 ? 0 . 1 f a v d d 33 ? 33 ? 33 ? 15 ? 15 ? 5 p f 15 p f 15 p f ad c v i n ? v i n + v c m ada 4930 - 1 1 1410-044 figure 44 . differential inpu t configuration using t he ada4930 - 1 for baseband applications where snr is a key parameter, differential transformer coupling is the recommended input configuration. an example is shown in figure 45. to bia s t he analog input, the vcm voltage can be conn ected to the center tap of the secondary winding of the transformer . 2 v p -p 49 . 9 ? 0 . 1 f r 1 r 1 c 1 ad c v i n + v i n ? v c m c 2 r 2 r 3 r 2 c 2 r 3 0 . 1 f 33 ? 1 1410-045 figure 45 . differential transformer - coupled configuration consider t he signal c haracteristics when selecting a transformer . most rf transformers saturate at frequencies below a few megahertz . e xcessive signal power can also cause core saturation , which leads to distortion. at input frequencies in the second nyquist zone and above, th e noise performance of most amplifiers is not adequate to achieve the true snr performance of the ad9683 . for applications where snr is a key parameter, differential double balun coupling is the re commended input configuration (see figure 46) . in this configuration, the input is ac - coupled and the vcm voltage is provided to each input through a 33 ? resistor. these resistors compensate for losses in the input baluns to provide a 50 ? impedance to the driver. adc r 1 0 . 1 f 0 . 1 f 2 v p -p v i n + v i n ? v c m c 1 c 2 r 1 r 2 r 2 0 . 1 f s 0 . 1 f c 2 33 ? 33 ? s p a p r 3 r 3 0 . 1 f 33 ? 1 1410-046 figure 46 . differential double balun input configuration in the double balun and transformer configurations, the value of the input capacitors and resistors is dependent on the input frequency and source impedance. based on these parameters , the value of the input resistors and capacitors may need to be adjusted or some components may need to be removed. table 9 displays recommended values to set the rc network for different input frequency ranges. however, these values are dependent on the input signal and bandwidth . use these values only as a starting gu ide. note that the values given in table 9 are for the r1, r2, c1, c2, and r3 component s shown in figure 45 and figure 46. table 9 . example rc network frequency range (mhz) r1 series (?) c1 differential (pf) r2 series (?) c2 shunt (pf) r3 shunt (?) 0 to 100 33 8.2 0 15 24 .9 100 to 4 0 0 15 8.2 0 8.2 24 .9 >400 15 3.9 0 3.9 24.9 an alternative to using a transformer - coupled input at frequencies in the second nyquist zone is to us e an amplifier with variable gain. the ad8375 digital variable gain amplifier (dvga ) provide s good performance for driving the ad9683 . figure 47 shows an example of the ad837 5 driving the ad9683 through a band - pass antialiasing filter . ad 837 5 adc 1 h 1 h 1 n f 1 n f vp o s v c m 15 p f 68 n h 2 0 k ? U2.5 p f 301 ? 165 ? 165 ? 5 . 1 p f 3 . 9 p f 180 n h 1000 p f 1000 p f n o t es 1 . a l l i ndu c t o r s ar e c oi l cra f t ? 0603 c s c o mp o n e n t s w i t h t h e ex c ep t io n o f t h e 1 h ch o k e i ndu c t o r s ( c o i l cra ft 0603 l s). 2 . f i l t er v a l u es s h o w n ar e f o r a 20 m h z band w i d t h f i l t er c e n t e r ed a t 140 m h z. 180 n h 220 n h 220 n h 1 1410-047 figure 47 . differential input configuration using the ad837 5 voltage reference a stable and accurate voltage reference is built into the ad9683 . the full - scale input range can be adjusted by varying the reference voltage via the spi . the input span of the adc tracks the reference voltage changes linearly.
data sheet ad9683 rev. 0 | page 21 of 44 clock input consider ations the ad9683 has two options for deriving the input sampling clock : a differential nyquist sampling clock input or an rf clock input (which is internally divided by 2 or 4 ). the clock input is selected in address 0x09 a nd by default is configured for the nyquist c lock input. for optimum performance, clock the ad9683 nyquist sample clock input, clk + and clk? , with a differential signal . the signal is typically ac - coupled into the clk+ and clk? pins via a transformer or via capacitors. these pins are biased internally (see figure 48 ) and require no external bias. i f the clock inputs are floated, clk? is pulled slightly lower than clk+ to prevent spurious clocking. nyquist clock input options the ad9683 nyquist c lock input supports a differential clock betwee n 40 mhz to 625 mhz. the clock input structure supports differential input voltages from 0.3 v to 3.6 v and is , therefore , compatible with various logic family inputs , such as cmos, lvds , and lvpecl. a sine wave input is also accepted, but higher slew rate s typically provide optimal performance. clock source jitter is a critical parameter that can affect performance, as described in the jitter considerations section. if the inputs are floated, pull the clk? pin low to prevent spurious clocking. the nyquist c lock input pin s, clk+ and clk ?, are internally biased to 0.9 v and have a typical input impedance of 4 pf in parallel with 10 k ? ( see figure 48) . the inpu t clock is typically ac - coupled to clk+ and clk ? . some typical clock drive circuits are presented in figure 49 through figure 52 for reference. a v d d c l k + 4 p f 4 p f c l k ? 0 . 9 v 1 1410-048 figure 48 . equivalent nyquist clock input circuit for application s where a single - ended low jitter clock between 40 mhz to 200 mhz is available, an rf t ransformer is recommended. an example using an rf transformer in the clock network is shown in figure 49 . at frequencies above 200 mhz, an rf balun is recommended, as seen in figure 50 . the back - to - back schottky diodes across the transformer secondary limit clock excursions in to the ad9683 to approximately 0.8 v p - p differential. this limit helps prevent the large voltage swings of the clock from feeding through to other portions of the ad9683 , yet preserves the fast rise and fall times of the clock, which are critical to low jitter performance. 390 p f 390 p f 390 p f s ch o tt k y d io d es: h sms 282 2 c l o c k i n p u t 50 ? 100 ? c l k ? c l k + ad c m i n i - c i rc u i ts ? ad t 1 - 1 wt , 1 : 1 z x f mr 1 1410-049 figure 49 . transformer - coupled differential clock (up to 200 mhz) 390 p f 390 p f 390 p f c l o c k i n p u t 1 n f 25 ? 25 ? c l k ? c l k + s ch o tt k y d io d es: h sms 282 2 ad c 1 1410-050 figure 50 . balun - coupled differential clock (up to 6 25 mhz) in some cases , it is desirable to buffer or generate multiple clock s from a single source. in those cases , analog devices , inc., offers clock drivers with excellent jitter performance. figure 51 shows a typical pecl d river circuit that u s e s pecl drivers such as the ad9510 , ad9511 , ad9512 , ad9513 , ad9514 , ad951 5 , ad9516 , ad9517 , ad9518 , ad9520 , ad9522 , ad9523 , ad9524 , and adclk905 , adclk907 , and adclk925 . 100 ? 0 . 1 f 0 . 1 f 0 . 1 f 0 . 1 f 240 ? 240 ? pe c l dr i ver 50k ? 50k ? c l k ? c l k + c l o c k i n p u t c l o c k i n p u t ad 95x x ad c 1 1410-051 figure 51 . different ial pecl sample clock (up t o 6 25 mhz) analog devices also offers lvds clock drivers with excellent jitter performance. a typical circuit is shown in figure 52. it uses lvds drivers such as the ad9510 , ad9511 , ad9512 , ad9513 , ad9514 , ad9515 , ad9516 , ad9517 , ad9518 , ad9520 , ad9522 , ad9523 , and ad9524 . 1 0 0 ? 0 . 1 f 0 . 1 f 0 . 1 f 0 . 1 f 50k ? 50k ? c l k ? c l k + c l o c k i n p u t c l o c k i n p u t ad 95x x l v d s dr i ver ad c 1 1410-052 figure 52 . differential lvds sample clock (up to 625 mhz)
ad9683 data sheet rev. 0 | page 22 of 44 rf clock input options the ad9683 rf c lock inp ut support s a single - ended clock between 625 m hz to 1.5 ghz. the equivalent rf c lock input circuit is shown in figure 53 . the input is self bias ed to 0.9 v and is typically ac - coupled. the input has a typical input impedance of 10 k ? in parallel with 0.5 pf at the rfclk pin. bias control 10k ? rfclk interna l clock driver 0.5pf 1 1410-053 figure 53 . equivalent rf clock input circuit it is recommended that the rf clock input of the ad9683 be dri ven with a pecl or sine wave signal with a minimum signal amplitude of 600 mv p - p . regardless of the type of signal being used, clock source jitter is of the most concern, as described in the jitter considerations section. figure 54 shows the preferred method of clocking when using the rf clock input on the ad9683 . it is recommended that a 50 ? tran smission line be used to route the clock signal to the rf clock input of the ad9683 due to the high frequency nature of the signal ; terminate the transmission line close to the rf clock input. rfclk ad c 50 ? tx line rf clock input 0.1 f 50 ? 1 1410-054 figure 54 . typical rf clock input circuit figure 56 shows the rf clock input of the ad9683 being driven from the lvpecl outputs of the ad9515 . the differential lvpecl output signal from the ad9515 is converted to a single - ended signal using an rf balun or r f transformer. the rf balun configuration is recommended for clock frequencies associated with the rf clock input. input clock divider the ad9683 contains an input clock divider with the ability to divide the nyquist input clock by integer values between 1 and 8. the rf clock input uses an on - chip predivider to divide the clock input by four before it reaches the 1 to 8 divider. this allows higher input frequencies to be achieved on the rf clock inp ut. the divide ratios can be selected using address 0x09 and address 0x0b. address 0x09 is used to set the rf clock input, and address 0x0b can be used to set the divide ratio of the 1 to 8 divider for both the rf clock input and the nyquist clock input. f or divide ratios other than 1, the duty cycle stabilizer (dcs) is automatically enabled. rfclk nyquist clock 1 to 8 divider 2 or 4 1 1410-055 figure 55 . clock divider circuit the ad9683 clock divider can be synchronized us ing the external sysref input. bit 1 and bit 2 of address 0x3a allow the clock divider to be resynchronized on every sysref signal or only on the first signal after the register is written. a valid sysref causes the clock divider to reset to its initial st ate. this synchro nization feature allows multiple parts to have their clock dividers aligned to guarantee simultaneous input sampling. clock duty cycle typical high speed adcs use both clock edges to generate a variety of internal timing signals and, as a result, may be sensitive to clock duty cycle. commonly, a 5% tolerance is required on the clock duty cycle to maintain dynamic performance characteristics . the ad9683 contains a dcs that retimes the nonsampling (falling ) edge, providing an internal clock signal with a nominal 50% duty cycle. this allows the user to provide a wide range of clock input duty cycles without affecting the performance of the ad9683 . jitter on the rising edge of the input clock is still of paramount concern and is not reduced by the dcs . the duty cycle control loop does not function for clock rates of less than 40 mhz nominally. the loop has a time constant asso ciated with it that must be considered when the clock rate can change dynamically . a wait time of 1.5 s to 5 s is required after a dynamic clock frequency increase or decrease before the dcs loop is relocked to the input signal. during the time that the loop is not locked, the dcs loop is bypassed, and the internal device timing is dependent on the duty cycle of the input clock signal. in such applications, it may be appropriate to disable the dcs . in all other applications, enabling the dcs circuit is re commended to maximize ac performance.
data sheet ad9683 rev. 0 | page 23 of 44 0 . 1 f 0 . 1 f 0 . 1 f 0 . 1 f lvpecl driver ad 95 15 127 v dd 82.5 127 82.5 clock input clock input rfclk ad c 50 ? tx line 0.1 f 50 ? 1 1410-056 figure 56 . differential pecl rf clock input circuit jitter considerations high speed, high resolution adcs are sensitive to the quality of the clock input. the degradation in snr at a giv en input frequency (f in ) due to jitter (t j ) can be calcu lated by snr hf = ?10 log[(2 f in t jrms ) 2 + 10 ) 10 / ( lf snr ? ] in the equation, the rms aperture jitter represents the root - mean - square of all jitter sources, which include the clock input, the analog input signal, and the adc aperture jitter specification. if undersampling applications are particularly sensitive to jitter, as shown in figure 57. 50 55 60 65 70 75 80 1 10 100 1000 snr (dbfs) input frequenc y (mhz) 0.05ps 0.2ps 0.5ps 1ps 1.5ps measured 1 1410-057 figure 57 . ad9683 - 250 snr v s. input frequency and jitter treat t he clock input as an analog signal in cases where aperture jitter may affect the dynamic range of the a d9683 . separate the p ower supplies for the clock drivers from the adc output driver supplies to avoid modulating the clock signal with digital noise. low jitter, crystal controlled oscillators make the best clock sources. if the clock is generated from an other type of source (by gating, dividing, or an other meth od ), retim e it using the original clock at the last step. refer to the an - 501 application note , aperture uncertainty and adc system perform ance , and the an - 756 application note , sampled systems and the effects of clock phase noise and jitter , for more information about jitter performance as it relates to adcs. power dissipation an d st andby mode as shown in figure 58 , the power dissipated by the ad9683 is proportional to its sample rate. the data in figure 58 w as taken using the same operating conditions as those used for the typical performance characteristics section . i dvdd in figure 58 is a summation of i dvdd and i drvdd . 0 0.05 0.10 0.15 0.20 0.25 0 0.1 0.2 0.3 0.4 0.5 40 55 70 85 100 1 15 130 145 160 175 190 205 220 235 250 supp l y current (a) t o t a l power (w) encode frequenc y (msps) i a vdd t o t a l power i dvdd 1 1410-058 figure 58 . ad9683 - 250 power vs. encode rate by asserting pdwn (either through the spi port or by asserting the pdwn pin high), the ad9683 is placed in power - d own mode . in this state, the adc typically dissipates about 9 mw. asserting the pdwn pin low returns the ad9683 t o its normal operati ng mode. low power dissipation in power - down mode is achieved by shutting down the reference, reference buffer, biasing networks, and clock. internal capacitors are discharged when entering power - down mode and then must be recharged when returning to nor mal operation. as a result, wake - up time is related to the time spent in power - down mode , and shorter power - down cycles result in proportion ally short er wake - up times. when using the spi port interface, the user can place the adc in power - down mode or standby mode. standby mode allows the user to keep the internal reference circuitry powered when faster wake - up times are required. see th e memory map register description s section and the an - 877 application note , interfacing to high speed adcs via spi , for additional details.
ad9683 data sheet rev. 0 | page 24 of 44 digital outputs jesd204b transmit top level d escription the ad9683 digital outp ut uses the jedec standard no. jesd204b, serial interface for data converters . jesd204b is a protocol to link the ad9683 to a digital processing device over a serial interface of up to 5 gbps link speeds. the benefits of the jesd204b interface include a reduction in required board area for data interface routing and the enabl ing of smaller packages for converter and logic devices. the ad9683 supports single lane interfaces. jesd204b overview the jesd204b data transmit block assembles the parallel data from the adc into frames and uses 8 b /10 b encoding as well as optional scrambling to form serial output data. lane synchronization is supported using special characters during the initial establishment of the link , and additional synchronization is embedded in the data stream thereafter. a matching external receiver is required to lock onto the serial data stream and recover the data and clock . fo r additional details on the jesd204b interface, refer to the jesd204b standard. the ad9683 jesd204b transmit block maps the output of the adc over a single link. the link is configured to use a sin gle pair of serial differential outputs that is called a lane . the jesd204b specification refers to a number of parameters to define the link , and these parameters must match between the jesd204b transmitter ( ad9683 output) and receiver. the jesd204b l ink is described according to the following parameters: ? s = samples transmitted per single converter per frame cycle ( ad9683 value = 1) ? m = n umber of converters per converter device ( ad9683 value = 1 ) ? l = number of lanes per converter device ( ad9683 value = 1) ? n = converter re solution ( ad9683 value = 14) ? n = total number of bits per sample ( ad9683 value = 16) ? cf = number of control words per frame clock cycle p er converter device ( ad9683 value = 0) ? cs = number of control bits/conversion sample (configurable on the ad9683 up to two bits) ? k = numbe r of frames per multiframe (configurable on the ad9683 ) ? hd = high density mode ( ad9683 value = 0) ? f = octets per frame ( ad9683 value = 2 ) ? c = control bit (overrange, overflow, underflow ; a vailable on the ad9683 ) ? t = tail bit (available on the ad9683 ) ? scr = scrambler enable/disable (configurable on the ad9683 ) ? fchk = checksum for the jesd204b parameters (automatically calculated and stored in register map) figure 59 shows a simplified block diagram of the ad9683 jesd204b link. t he ad9683 use s one converter and one lane. the c onverter data is output to serdout0 +/ serdout0 ? . by default , in the ad9683 , the 14 - bit converter word is divided into two octets ( eight bits of data). bit 0 ( msb ) through bit 7 are in the first octet , and th e second octet contains bit 8 throug h bit 13 ( lsb ) and two tail bits. the tail bits can be configured as zeros, a pseudorandom number sequence , or control bits indicating overrange, underrange , or v alid data conditions. the two resulting octets can be scrambled. scrambling is optional ; howev er, it is available to avoid spectral peaks when transmitting similar digital data patterns. the scrambler uses a self synchronizing , polynomial - based algorithm defined by the 1 + x 14 + x 15 equation . the descrambler in the receiver should be a self - synchro nizing version of the scrambler polynomial. the two octets are then encoded with an 8 b /10 b encoder. the 8 b /10 b encoder works by taking eight bits of data (an octet) and encoding them into a 10 - bit symbol. figure 60 sh ows how the 14- bit data is taken from the adc, the tail bits are added, the two octets are scrambled, and how the octets are encoded into two 10- bit symbols. figure 60 illustrates the default data format. at the data l ink layer, in addition to the 8 b /10 b encoding, the character replacement is used to allow the receiver to monitor frame alignment. the c haracter replacement process occurs on the frame and multiframe boundaries , and implementation depends on which boundary is occurring , and if scrambling is enabled. if scrambling is disabled, the following applies : ? if the last scrambled octet of the last frame of the multi frame equals the last octet of the previous frame, the transmitter replaces the last octet with the c ontrol character /a/ = /k28.3/. ? on other frames within the multiframe, if the last octet in the frame equals the last octet of the previous frame, the transmitter replaces the last oct et with the control character /f / = /k28.7/. if scrambling is enabled, t he following applies : ? if the last octet of the last frame of the multiframe equals 0x7c, the transmitter replaces the last octet with the control character /a/ = /k28.3/. ? on other frames within the multiframe, if the last octet equals 0xfc, the transmitt er replaces the last oct et with the control character /f / = /k28.7/. refer to jedec standard no. 204b , july 2011 for additional information about the jesd204b interface. section 5.1 covers the transport layer and data format details and section 5.2 covers scrambling and descrambling .
data sheet ad9683 rev. 0 | page 25 of 44 jesd204b synchronization details the ad9683 is a jesd204b subclass 1 device that establishes synchronization of the link through two control signals, sysref and sync, and typically a common device clock. sysref and sync are common to all converter devices for alignment purposes at the system level. the synchronization process is accomplished over three phases: code group synchronization (cgs), initial lane alignment s equenc e (ilas) , and data transmission . i f scrambling is enabled, the bit s are not actually scrambled until the data transmission phase, and the cgs phase and ilas phase do not use scrambling. cgs phase in th e cgs phase, the jesd204b transmit block transmit s /k28.5/ characters. the receiver (external logic device) must locate / k28.5 / characters in its input data stream using clock and data recover y (cdr) techniques. when a certain number of consecutive / k28.5 / characters are detected on the link lane , the re ceiver initiate s a sysref edge so that the ad9683 transmit data establishes a local multifra me clock (lmfc) internally. the sysref edge also resets any sampling edges within the adc to align sampl ing instances to the lmfc. this is important to maintain synchronization across multiple devices. the receiver or logic device deassert s the sync signal (syncinb ) , and the transmitter block begin s the ilas phase. ilas phase in th e ilas phase, the transmi tter send s out a known pattern , and the receiver align s the lane s in the link and verif ies the parameters of the link. the ilas phase begins after sync has been deasserted (goes high). the transmit block begin s to transmit four multiframes. dummy samples are inserted between the required characters so that full multiframes are transmitted. the four multiframes include the following: ? multi f rame 1 b egins with a n /r/ character [k28.0] and ends with an /a/ character [k28.3]. ? multi f rame 2 b egins with an /r/ cha racter followed by a /q/ [k28.4] character, followed by link configuration parameters over 14 configuration octets (see table 10) , and ends with an /a/ character. ? multi f rame 3 i s the same as multi frame 1 . ? multi f ra me 4 i s the same as multi frame 1 . data transmission phase in th e data transmission phase, frame alignment is monitored with control characters. character replacement is used at the end of frames. character replacement in the transmitter occurs in the follo wing instances: ? if scrambling is disabled and the last octet of the frame or multiframe equals the octet value of the previous frame. ? i f scrambling is enabled and the last octet of the multiframe is equal to 0x7c , or the last octet of a frame is equal to 0 xfc. table 10. fourteen configuration o ctets of the ilas phase no. bit 7 ( msb ) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ( lsb ) 0 did [ 7:0 ] 1 bid [ 3:0 ] 2 lid [ 4:0 ] 3 scr l[4:0] 4 f [ 7:0 ] 5 k [ 4:0 ] 6 m [ 7:0 ] 7 cs [ 1:0 ] n [ 4:0 ] 8 subclass [ 2:0 ] n[ 4:0 ] 9 jesdv [ 2:0 ] s[ 4:0 ] 10 cf [ 4:0 ] 11 r eserved , dont c are 12 reserved, d ont c are 13 fchk [ 7:0 ] link setup parameters the following sections demonstrate how to configure the ad9683 jesd204b interface. the steps to configure the output include the following: 1. d isable the lane before changing the configuration . 2. s elect a quick configuration option . 3. configure detailed options . 4. check fchk, the checksum of the jesd204b interface parameters . 5. s et additional digital output configuration options . 6. r e - enable the lane . disable l ane before changing configuration before modifying the jesd204b link parameters, disable the link and h o ld it in reset. this is accomplished by writin g l ogic 1 to address 0x5f , bit 0 . configure detailed options configure the t ail b its and c ontrol bits as follows . ? with n = 16 and n = 14, there are two bits available per sample for transmitting additional information over the jesd204b link. the option s are tail bits or control bits. by default, tail bits of 0b00 value are used. ? tail bits are dummy bits sent over the link to complete the two octets and do not convey any information about the input signal. tail bits can be fixed zeros (default) or pseudo - random numbers ( address 0x5f , bit 6 ). ? one or two control bits can be used instead of the tail bits through address 0x72 , bits[ 7:6 ] . the tail bits can be set using address 0x14 , bits[ 7:5 ] , and the tail bits can be enabled using address 0x5f, bit 6 . set l ane identification values . ? jesd204b allows parameters to identify the d evice and l ane. these parameters are transmitted during the ilas phase , and they are accessible in the internal registers.
ad9683 data sheet rev. 0 | page 26 of 44 ? there are three identification values : d evice identification (did ), b ank identification (bid ) , and l ane identification (lid ). did and bid are device specific ; therefore , they can be used for link identification. set the n umber of frames per m ultiframe, k . ? per the jesd204b specification, a multiframe is defined as a group of k successive frames, where k is between 1 and 32, and it requires that the number of octets be between 17 and 1024. the k value is set to 32 by default in address 0x70 , bits [ 7 :0 ] . note that the k value is the register value plus 1. ? the k value ca n be changed ; however, it must comply with a few conditions. the ad9683 uses a fixed value for octets per frame ( f ) based on the jesd204b quick configuration setting. k must also be a multiple of 4 and conform to the following equation : 32 k c eil (17/ f ) ? the jesd204b specification also requires the number of octets per multiframe (k f) to be between 17 and 1024. the f value is fixed through the quick configuration setting to ensure that this relationship is true. table 11. jesd204b configurable identification values id value register , bits value r ange lid 0x67 , [ 4:0 ] 0 to 31 did 0x64 , [ 7:0 ] 0 to 255 bid 0x65 , [ 3:0 ] 0 to 15 scramble, scr . ? scrambling can be enabled or disabled by setting address 0x6e , bit 7. by default, scrambling is enabled. per the jesd204b protocol, scrambling is functional only after the l ane synchronization has completed. select l ane synchronization o ptions . most of the synchronization features of the jesd204b interface are enabled , by defa ult , for typical applications. in some cases, these features can be disabled or modified as follows : ? ilas enabling is controlled in address 0x5f , bits [ 3:2 ] and , by default , is enabled. optionally, to support some unique instances of the interfaces (such as nmcda - sl), the jesd204b interface can be programmed to either disable the ilas sequence or continually repeat the ilas sequence . the ad9683 has fixed values of some of the jesd204b interface para meters , and they are as follows: ? n = 14 , number of bits per converter is 14 in address 0x72 , bits [ 3 :0 ] ? n = 16, number of bits per sample is 16 in address 0x73 , bits [ 3 :0 ] ? cf = 0 , number of control words per frame clock cycle per converter is 0 in address 0x75 , bits [ 4:0 ] ve rif y r ead only values: l anes per link (l) , octets per frame (f) , number of converters (m), and samples per converter per frame ( s ). the ad9683 calculates values for some jesd204 b parameters based on other setting s , particularly the quick configuration register selection. the read only values here are available in the register map for verification. ? l = l anes per link is 1 ; read the values from address 0x6e , bit s [4:0] ? f = o ctets pe r frame is 1, 2 , or 4 ; read the value from address 0x6f , bits [ 7 :0 ] ? hd = h igh d ensity mode can be 0 or 1 ; read the value from address 0x75 , bit 7 ? m = n umber of c onverters per link is 1 ; read the value from address 0x71 , bit s[ 7: 0 ] ? s = s amples per converte r per frame can be 1 or 2 ; read the value from address 0x74 , bit s[ 4: 0 ] check fchk, checksum of jesd204b interface parameters the jesd204b parameters can be verified through the checksum value ( fchk ) of the jesd204b interface parameters. each lane has a fch k value associated with it. the fchk value is transmitted during the ilas secon d m ultiframe and can be read from the internal registers. the c hecksum value is the modulo 256 sum of the parameters listed in the no. column of table 12 . the c hecksum is calculated by adding the parameter fields before they are packed into the octets shown in table 12 . the fchk value for the lane configuration for data coming out of the lane 0 ca n be read from address 0x79 . table 12. jesd204b configuration t able u sed in ilas and chksum c alculation no. bit 7 ( msb ) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ( lsb ) 0 did [ 7:0 ] 1 bid [ 3:0 ] 2 lid [ 4:0 ] 3 scr l[4:0] 4 f [ 7:0 ] 5 k [ 4:0 ] 6 m [ 7:0 ] 7 cs [ 1:0 ] n [ 4:0 ] 8 subclass [ 2:0 ] n[ 4:0 ] 9 jesdv [ 2:0 ] s[ 4:0 ] 10 cf [ 4:0 ] set additional digital output configuration options other data format controls include the following: ? invert polarity of serial output data , addre ss 0x60 , bit 1 ? adc d ata format select ( offset binary or twos complement) , address 0x14 , bits [ 1:0 ] ? options for interpreting signal on sysref and sync inb , address 0x3a , bits[ 4 : 0 ]
data sheet ad9683 rev. 0 | page 27 of 44 re e nable lane after configuration after modifying the jesd204b link paramet ers, enable the link so that the synchronization process can begin. this is accomplished by writing logic 0 to address 0x5f, bit 0. converter converter input sysref syncinb converter sample ad9683 adc serdout0 jesd204b lane control (m = 1, l = 1) 1 1410-059 figure 59 . transmit link simplified block diagram 8b/10b encoder/ character replacement serializer t . . . sync sysref vin+ vin? serdout0 adc test pattern 16-bit jesd204b test pattern 8-bit adc a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a0 octet0 octet1 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 c0 c1 s0 s1 s2 s3 s4 s5 s6 s7 s8 s9 s10 s11 s12 s13 s14 s15 e0 e1 e2 e3 e4 e5 e6 e7 e10 e11 e12 e13 e14 e15 e16 e17 e8 e9 e0 e1 e2 e3 e4 e5 e6 e7 e8 e9 e18 e19 e19 optional scrambler 1 + x 14 + x 15 jesd204b test pattern 10-bit 1 1410-060 figure 60 . dig ital processing of jesd204b lane table 13. jesd204b typical configurations jesd204b configure s etting m ( no. of c onverters) , address 0x71 , bit s [ 7: 0 ] l ( no. of lanes) , address 0x6e , bit s [ 4: 0 ] f ( octets/frame ) , address 0x6f , bit s [ 7:0 ] , r ead o nly s (samples/adc/frame) , address 0x74 , bits [ 4:0 ] , r ead o nly hd (high density mode) , address 0x75 , bit 7 , r ead o nly 0x11 (default) 1 1 2 1 0 data from adc frame assembler (add tail bits) optional scrambler 1 + x 14 + x 15 8b/10b encoder to receiver 1 1410-061 figure 61 . adc output data path table 14. j esd204b frame alignment monitoring and correction replacement characters scrambling lane synchronization character to be replaced last octet in multiframe replacement character off on last octet in frame repeated from previous frame no k28.7 off on last octet in frame repeated from previous frame yes k28.3 off off last octet in frame repeated from previous frame not applicable k28.7 on on last octet in frame equals d28.7 no k28.7 on on last octet in frame equals d28.3 yes k28.3 on off last octet in frame equals d28.7 not applicable k28.7
ad9683 data sheet rev. 0 | page 28 of 44 frame and lane alignment monitoring and correction frame alignment monitoring and correction is part of the jesd204b specification . the 14 - bit word requires two octets to transmit all the data. the two octet s (msb and lsb), where f = 2, make up a frame. during normal operating conditions , frame alignment is monitored via alignment characters, which are inserted under certain conditions at the end of a frame. table 14 summarizes the conditions for character insertion along with the expected characters under the various operation modes. if lane synchronization is enabled, the replacement character value depends on whether the octet is at the end of a frame or at the end of a multiframe. based on the operating mode, the receiver can ensure that it is still synchronized to the frame boundary by correctly receiving the replacement characters. digital outputs and timing the ad9683 has differential digital outputs that power up by default. t he driver current is derived on chip and sets the output current at each output equal to a nominal 3 ma. each output presents a 100 ? dynamic internal termination to reduce unwanted reflections. place a 100 ? differential termination resistor at each receiver input to result in a nominal 6 00 mv p - p swing at the receiver (see fi gure 62 ). alternatively, single - ended 50 ? termination can be used. when single - ended termination is used, the termination voltage must be drvdd/2; otherwise, ac coupling capacitors can be used to terminate to any single - ended voltage. 100? or 100? differential trace pair serdout0+ drvdd v rxcm serdout0? v cm = rx v cm output swing = 600mv p-p 0.1f 0.1f receiver 1 1410-062 fi gure 62 . ac - coupled digital output termination example the ad9683 digital outputs can interface with custom asics and fpga receivers, providing superior switching perfor mance in noisy environments. single point - to - point network topologies are recommended with a single differential 100 ? termination resistor placed as close to the receiver logic as possible. the common mode of the digital output automatically biases itself to half the supply of the ad9683 (that is, the common - mode voltage is 0.9 v for a supply of 1.8 v) if a dc - coupled connecti on is used (see figure 63 ). for a receiver logic that is not within the bounds of the drvdd supply, use a n ac - coupled connection. simply place a 0.1 f capacitor on each output pin and derive a 100 ? differential termination close to the receiver side. 100? 100? differentia l trace p air d r vdd v cm = d r vdd/2 output swing = 600mv p-p receiver serdout0+ serdout0? 1 1410-063 figure 63 . dc - coupled digital output termination example if there is no far - end receiver termination , or if there is poor differential trace routing, timing errors may resu lt. to avoid such timing errors, it is recommended that the trace length be less than six inches , and that the differential output traces be close together and at equal lengths. figure 64 show s an example of the d igital output (default) data eye and time interval error (tie) jitter histogram and bathtub curve for the ad9683 lane running at 5 gbps . additional spi options allow the user to further increase t he output driver voltage swing or enable preemphasis to drive longer trace lengths (see address 0x15 in table 17 ). t he power dissipation of the drvdd supply increases when this option is used. see the memory map section for more details. the format of the output data is twos complement by default. to change the output data format to offset binary, see the memory map section ( address 0x14 in table 17).
data sheet ad9683 rev. 0 | page 29 of 44 0 ? 0 . 5 0 . 5 uls pe r i o d 1 : h i s t o g r a m 6000 7000 ?10 0 time (ps) 10 5000 4000 1000 0 2000 3000 1 ?16 1 ?14 1 ?12 1 ?10 1 ?8 1 ?6 1 ?4 1 ?2 1 ber 3 ? 2 ? ?100 ?200 0 100 200 t i me ( p s ) 400 300 200 100 0 ?100 ?300 ?400 ?200 voltage (mv) h e i g h t 1 : eye d i a g r a m 1 ? t j a t ber1: b athtub hits ey e: all bits offset: 0 uls: 7000; 993329 total: 7000; 993329 1 1410-064 figure 64. ad9683 digital outputs data eye, histogram and bathtub, external 100 ? terminations at 5 gbps 0 ? 0 . 5 0 . 5 uls pe r i o d 1 : h i s t o g r a m 6000 7000 ?10 0 time (ps) 10 5000 4000 1000 0 2000 3000 1 ?16 1 ?14 1 ?12 1 ?10 1 ?8 1 ?6 1 ?4 1 ?2 1 ber 3 ? 2 ? ?50 ?150 ?250 0 50 250 150 t i me ( p s ) 400 300 200 100 0 ?100 ?300 ?400 ?200 voltage (mv) h e i g h t 1 : eye d i a g r a m 1 ? t j at ber1: b athtub hits ey e: all bits offset: 0.0018 uls: 8000; 673330 total: 8000; 673330 1 1410-065 figure 65 . ad9683 digital outputs data eye, histogram and bathtub, external 100 ? terminations at 3.4 gbps adc overrange and ga in control in receiver applications, it is desirable to have a mechanis m to reliably determine when the converter is about to be clipped. the standard overflow indicator provides delayed information on the state of the analog input that is of limited value in preventing clipping. therefore, it is helpful to have a programmabl e threshold below full scale that allows time to reduce the gain before the clip occurs. in addition, because input signals can have significant slew rates, latency of this function is of concern. using the spi port, the user can provide a threshold above which the fd output is active. bit 0 of address 0x45 enables the fast detect feature. address 0x4 7 to address 0x4 a allow the user to se t the threshold level s . as long as the signal is below the selected threshold, the fd output remains low. in this mode, t he magnitude of the data is considered in the calculation of the condition, but the sign of the data is not considered. the threshold detection responds identically to positive and negative signals outside the desired range (magnitude). adc overrange (or) the adc overrange indicator is asserted when an overrange is detected on the input of the adc. the overrange condition is determined at the output of the adc pipeline and, therefore, is subject to a latency of 36 adc clock cycles. an overrange at the input is indicated by this bit 36 clock cycles after it occurs. gain switching the ad9683 includes circuitry that is useful in applications either where large dynamic ranges exist or where gain ranging amplifiers are employed. this circuitry allows digital thresholds to be set such that an upper threshold and a lower threshold can be programmed. one such use is to detect when an adc is about to reach full scale with a particular input condition. the resu lt is to provide an indicator that can be used to quickly insert an attenuator that prevents adc overdrive.
ad9683 data sheet rev. 0 | page 30 of 44 fast threshold detection (fd ) the fd indicator is asserted if the input magnitude exceeds the value programmed in the fast detect upper threshold register s, located in address 0x47 and address 0x48. the selected threshold register is compared with the signal magnitude at the output of the adc. the fast upper threshold detection has a latency of seven clock cycles. the approximate upper threshold mag nitude is defined by upper threshold magnitude (dbfs) = 20 log ( threshold magnitude /2 1 3 ) the fd indicators are not cleared until the signal drops below the lower threshold for the programmed dwell time. the lower threshold is programmed in the fast detect lower threshold register s , located at address 0x49 and address 0x4a. the fast detect lower threshold register is a 1 6 - bit register that is compared with the signal magnitude at the output of the adc. this comparison is subject to the adc pipeline latency but is accurate in terms of converter resolution. the lower threshold magnitude is defined by lower threshold magnitude (dbfs) = 20 log ( threshold magnitude /2 1 3 ) for example, to set an upper threshold of ? 6 dbfs, write 0x0fff to those registers , and to set a lower threshold of ? 10 dbfs, write 0x0a1d to those registers. the dwell time can be programmed from 1 to 65,535 sample clock cycles by placing the desired value in the fast detect dwell time register s, located in address 0x4b and address 0x4c. the operation of the upper threshold and lower threshold registers, along with the dwell time registers , is shown in figure 66. upper threshold lower threshold fd midscale dwell time timer reset by rise above lower threshold timer completes before signal rises above lt dwell time 1 1410-066 figure 66 . th reshold settings for fd signals
data sheet ad9683 rev. 0 | page 31 of 44 dc c orrection (dcc) because the dc offset of the adc may be significantly larger than the signal being measured, a dc correction circuit is included to null the dc offset before measuring the power. the dc correction circ uit can also be switched into the main signal path ; however, this may not be appropriate if the adc is digitizing a time - varying signal with significant dc content, such as gsm. dc correction bandwi dth the dc correction circuit is a high - pass filter with a programmable bandwidth (ranging between 0.29 hz and 2.387 khz at 245.76 msps). the bandwidth is controlled by writing to the four dc correction bandwidth select bits , located at address 0x40, bits[5:2]. the following equation can be used to compute the bandwidth value for the dc correction circuit: dc_corr_bw = 2 ? k ?14 f clk /(2 ) where: k is the 4 - bit value programmed in bits[5:2] of address 0x40 (values between 0 and 13 are valid for k ). f clk is the ad9683 adc sample rate in hertz. dc correction readba ck the current dc correction value can be read back in address 0x41 and address 0x42. the dc correction value is a 16 - bit value that can span the entire input range of the adc. dc correction freeze setting bit 6 of address 0x40 freezes the dc correction at its current state and continues to use the last updated value as the dc correction value. clearing this bit restarts dc correction and adds the currently calculated value to the data. dc correction enable bi ts setting bit 1 of address 0x40 enables dc correction for use in the output data signal path.
ad9683 data sheet rev. 0 | page 32 of 44 serial port interfac e (spi) the ad9683 spi allows the user to configure th e converter for specific functions or operations through a structured register space provided inside the adc. the spi gives the user added flexibility and customization, depending on the application. addresses are accessed via the serial port and can be wr itten to or read from via the port. memory is organized into bytes that can be further divided into fields. these fields are documented in the m emory ma p section. for detailed operational information , see the an - 877 application note , interfacing to high speed adcs via spi . configuration using the spi three pins define the spi of this adc: the sclk pin , the sdio pin , and the cs pin (s ee table 15 ). the sclk (serial clock) pin is used to synchronize the read and write d ata presented from/to the adc. the sdio (seri al data input/output) pin is a dual - purpose pin that allows data to be sent to and read from the internal adc memory map registers. the cs (chip select bar) pin is an active low control that enables or disab les the read and write cycles. table 15. serial port interface pins pin function sclk serial clock . the serial shift clock input, which is used to synchronize the serial interface reads and writes. sdio serial data i nput/ o utput. a dual - purpose pin that typically serves as an input or an output, depending on the instruction being sent and the rel ative position in the timing frame. cs chip select bar . an active low control that gates the read and write cycles. the falling edge of cs , in conjunction with the rising edge of sclk, determines the start of the fra ming. an example of the serial timing and its definitions can be found in figure 67 and table 5 . other modes involving cs are available. cs can be held low indefinitely, which permanently enables the device; this is called streaming. cs can stall high between bytes to allow for additional external timing. when cs is tied high, spi functions are placed in a high impedance mode. this mode turns on any spi pin secondary functions. during an instruction phase, a 16 - bit instruction is transmitted. data follows the instruction phase, and its length is determined by the w0 and the w1 bit s. all data is com posed of 8 - bit words. the first bit of each individual byte of serial data indicates whether a read or write command is issued. this allows the sdio pin to change direction from an input to an output. in addition to word length, the instruction phase deter mines whether the serial frame is a read or write operation, allowing the serial port to be used both to program the chip and to read the contents of the on - chip memory. if the instruction is a readback operation, performing a readback causes the sdio pin to change direction from an input to an output at the appropriate point in the serial frame. data can be sent in msb first mode or in lsb f irst mode. msb first is the default on power - up and can be changed via the spi port configuration register. for more information about this and other features, see the an - 877 application note , interfacing to high speed adcs via spi . hardware interface the pins described in table 15 comp ri se the physical interface between the user programming device and the serial port of the ad9683 . the sclk pin and the cs pin function as inputs when using the spi interface. the sdio pin is bidirectional, functioning as an input during write phases and as an output during readback. the spi interface is flexible enough to be controlled by either fpgas or microcontrollers. one method for spi configuration is describe d in detail in the an - 812 application note , microcontroller - based serial port interface (spi) boot circuit . do not activate t he spi port during periods when the full dynamic performance of the con verter is required. because the sclk signal, the cs signal, and the sdio signal are typically asynchronous to the adc clock, noise from these signals can degrade converter performance. if the on - board spi bus is used for other devices, it may be necessary to provide buffers between this bus and the ad9683 to prevent these signals from transitioning at the converter inputs during critical sampling periods.
data sheet ad9683 rev. 0 | page 33 of 44 spi accessible features table 16 provides a brief description of the general features that are accessible via the spi. these features are described in detail in the an - 877 application note , interfacing to high speed adcs via s pi . the ad9683 part - specific features are described in the memory map register description s section . table 16 . features accessible using the spi feature name description mode allows the user to set either power - down mode or standby mode clock allows the user to access the dcs via the spi offset allows the user to digital ly adjust the converter offset test i/o allows the user to set test modes to have known data on output bits output mode allows the user to set up outputs output phase allows the user to set the output clock polarity output delay allows the user to vary the dco delay vref allows the user to set the reference voltage don?t care don?t care don?t care don?t care sdio sclk cs t s t dh t clk t ds t h r/w w1 w0 a12 a11 a10 a9 a8 a7 d5 d4 d3 d2 d1 d0 t low t high 1 1410-067 figure 67 . serial port interface timing diagram
ad9683 data sheet rev. 0 | page 34 of 44 m emory ma p reading the memory m ap register table each row in the memory map register table has eight bit locati ons. the memory map is roughly divided into three sections: the chip configuration registers (address 0x00 to address 0x02); the adc functions registers, including setup, control, and te st (address 0x08 to address 0x a8 ) ; and the device update register (add ress 0xff) . the memory map register table (see table 17 ) documents the default hexadecimal value for each hexadecimal address shown. the column with the heading bit 7 (msb) is the start of the default hexadecimal value given. for example, address 0x1 4 , the output mode register, has a h exadecimal default value of 0x0 1 . this means that bit 0 = 1 , and the remaining bits are 0s. this setting is the default output format value , which is twos compl e ment . for more informa tion on this function and others, see the an - 877 application note , interfacing to high speed adcs via spi . this application note details the functions controlled by address 0x00 to address 0x 2 1 and address 0xff , with the exception of address 0x08 and address 0x14 . the remaining registers, address 0x08, address 0x14, and address 0 x 3a through address 0x a8 , are documented in th e memory map register description s section. open and reserved locations all address and bit locations that are not included in table 17 are not currently supported for this device. write u nused bits of a valid address location with 0s. writing to these locations is required only when part of an address location is open (for example, address 0x18). if the entire address location is open (for example, address 0x13), do not write to this address location . default values after the ad9683 is reset, critical registers are loaded with default v alues. the default values for the registers are given in the memory map register table (see table 17) . logic levels an explanatio n of logic level terminology follows: ? bit is set is synonymous with bit is set to logic 1 or writing logic 1 for the bit. ? clear a bit is synonymous with bit is set to logic 0 or writing logic 0 for the bit. transfer register map address 0x0 9, address 0x0b, address 0x14, address 0x18, and address 0x3a to address 0x4c are shadowed. writes to these addresses do not affect part operation until a transfer command is issued by writing 0x01 to address 0xff, setting the transfer bit. this allows these registers to be updated internally and simultaneously when the transfer bit is set. the internal update takes place when the transfer bit is set, and then the bit autoclears.
data sheet ad9683 rev. 0 | page 35 of 44 memory map register table all address and bit locations that are not inc luded in table 17 are not currently supported for this device. table 17 . memory map registers reg addr (hex) reg addr name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) defaul t notes 0x00 spi p ort configuration 0 lsb f irst soft r eset 1 1 soft r eset lsb f irst 0 0x18 0x01 chip id ad9683 8 - bit chip id is 0x c3 0x c3 read o nly 0x02 chip grade speed g rade : 00 = 250 msps , 11 = 170 msps reserved for chip die revision , currently 0x0 0x00 o r 0x30 0x08 pdwn m odes external pdwn m ode : 0 = pdwn is full power - down , 1 = pdwn puts device in standby j esd204b s t an dby mode (when external pdwn is used) : 0 = jesd204b core is unaffec ted , 1 = jesd204b core is powered down except for pll jesd204b power modes : 00 = normal m ode (power - up) ; 01 = power - down mode , pll off, s erializer off, clocks stopped, digital held in reset ; 10 = standby m ode , pll on, s erializer off, clocks stopped, digit al circuitry held in reset adc power modes : 00 = normal mode (power - up) , 01 = power - down mode , 10 = standby m ode , d oes not affect jesd204b digital circuitry 0x00 0x09 global c lock r eserved clock s election: 00 = n yquist c lock , 01 = rf clock divide by 2 , 10 = rf c lock divide by 4 , 11 = clock off clock duty cycle stabilizer enable 0x01 dcs enabled if c lock divider enabled 0x0a pll s tatus pll locked status jesd 204b l ink is ready read o nly 0x0b clock divide clock divide phase relative to the e ncode clock : 0x0 = 0 input clock cycles delayed , 0x1 = 1 input clock cycles delayed , 0x2 = 2 input clock cycles delayed , 0x7 = 7 input clock cycles delayed clock divider ratio relative to the encode clock : 0x00 = d ivide by 1 , 0x01 = d ivide by 2 , 0x02 = d ivide by 3 , 0x 0 7 = d ivide by 8 0x00 clock divide values other than 0x00 automatically cause the dcs to become active 0x0d test mode u ser test mode cycle : 00 = repeat pattern (u ser pattern 1, 2, 3, 4, 1, 2, 3, 4 , 1, ) ; 10 = s ingle pattern (u ser patte rn 1, 2, 3, 4, then all zeros) long pseudo - random number generator reset : 0 = l ong prn enabled , 1 = l ong prn held in reset short pseudo - random number generator reset : 0 = s hort prn enabled , 1 = s hort prn held in reset data output test generation mode : 0000 = off (normal mode ) , 0001 = m idscale short , 0010 = p ositive f ull scale , 0011 = n egative full scale , 0100 = alternating checkerboard , 0101 = pn s equence l ong , 0110 = pn s equence s hort , 0111 = 1/0 word toggle , 1000 = user test mode (use with addres s 0x0d , b it s [ 7 :6 ] and u ser pattern 1, 2, 3, 4) , 1001 to 1110 = u nused , 1111 = ramp output 0x00 0x10 customer o ffset offset a djust in lsbs from +31 to ? 32 (twos complement format) : 01 1111 = a djust output by +31 , 01 1110 = a djust output by +30 , 0 0 0001 = a djust output by +1 , 00 0000 = a djust output by 0 ( d efault ), 10 0001 = a djust output by ? 31, 10 0000 = a dju s t output by ? 32 0x00
ad9683 data sheet rev. 0 | page 36 of 44 reg addr (hex) reg addr name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) defaul t notes 0x14 output m ode jesd204b cs bits assignment (in conjunction with address 0x72) : 000 = { o verrange|| u nderrange, v alid} , 001 = { o verrange, u nderrange} , 010 = { o verrange|| u nderrange, b lank} , 011 = {blank, valid} , 100 = {blank, blank} , 101 = {underrange, overrange} , 110 = {valid, overange||underrange} , 111 = {valid, blank } adc output disable adc data invert : 0 = n orm al (default) , 1 = i nverted d ata format select (dfs) : 00 = o ffset b inary , 01 = twos complement 0x01 0x15 cml output adjust jesd204b cml differential output drive level adjustment : 000 = 75 % of nominal ( 438 mv p - p ) , 001 = 8 3 % of nominal ( 488 mv p - p ) , 010 = 9 1 % of nominal ( 538 mv p - p ) , 011 = nominal ( default ) ( 588 mv p - p ) , 1 0 0 = 1 09 % of nominal ( 638 mv p - p ) , 101 = 117% of nominal ( 690 mv p - p ) , 110 = 126% of nominal ( 740 mv p - p ) , 111 = 134% of nominal ( 790 mv p - p ) 0x03 0x18 input span select m ain reference full - scale vref adjustment : 0 1111 = internal 2.087 v p - p , 0 0001 = internal 1.772 v p - p , 0 0000 = internal 1.75 v p - p ( d efault ) , 1 1111 = internal 1.727 v p - p , 1 0000 = internal 1.383 v p - p 0x00 0x19 user test pattern 1 l sb user test p attern 1 lsb ; u se in conjunction with address 0x0d and address 0 x61 0x1a user test pattern 1 m sb user test pattern 1 msb 0x1b user test pattern 2 l sb user test pattern 2 lsb 0x1c user test patter n 2 m sb user test pattern 2 msb 0x1d user test pa ttern 3 l sb user test pattern 3 lsb 0x1e user test pattern 3 m sb user test pattern 3 msb 0x1f user test pattern 4 l sb user test pattern 4 lsb 0x20 user test pattern 4 m sb user test pattern 4 msb 0x21 pll low encode 00 = f or lane speeds of >2 gbps , 01 = f or lane speeds of <2 gbps 0x00 0x3a syncinb/ sysref c ontrol jesd204b realign syncinb : 0 = normal mode , 1 = realign s lane on every active syncinb jesd204b realign sysref : 0 = normal mode , 1 = realign s lane on every active sysref sysref m ode : 0 = c ontinuous reset clock dividers , 1 = s ync on next sysref rising edge only sysref enable : 0 = disabled , 1 = enabled enable syncinb buffer : 0 = buffer disabled , 1 = buffer enabled 0x00
data sheet ad9683 rev. 0 | page 37 of 44 reg addr (hex) reg addr name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) defaul t notes 0x40 dc correction control freeze dc correction : 0 = calculate , 1 = freeze value dc correction bandwidth select; correction bandwidth is 2387.32 hz/reg ister val ue ; there are 14 possible values ; 0000 = 2387.32 hz , 0001 = 1193.66 hz , 0010 = 596.83 hz , 0011 = 298.42 hz , 0100 = 149.21 hz , 0101 = 74.60 hz , 0110 = 37.30 hz , 0111 = 18.65 hz , 1000 = 9.33 hz , 1001 = 4.66 hz , 1010 = 2.33 hz , 1011 = 1.17 hz , 1100 = 0.58 hz , 1101 = 0.29 hz , 1110 = reserved , 1111 = reserved enable dc correction 0 x 00 0x41 dc c orrection v alue 0 dc correction value lsb [7:0] 0x00 0 x42 dc c orrection v alue 1 dc correction value msb [15:8] 0x00 0x45 fast detect control fd p in f unction : 0 = fast detect , 1 = o verrange force fd o utput enable : 0 = normal function , 1 = force to value force d fd output value ; if force fd pin is true, th is value is output on the fd p in enable fast detect output 0x00 0x47 fast detect upper threshold fast detect upper threshold[7:0] 0x48 fast detect upper threshold[14:8] 0x49 fast detect lower threshold fast detect lower threshold[7:0] 0x4a fast detect lower threshold[14:8] 0x4b fast detect dwell time fast detect dwell time[7:0] 0x4c fast detect dwell time[15:8] 0x5e jesd 204b quick config jesd204b q uick configuration, always reads back 0x00; 0x11 : m = 1, l = 1; one converter, one la ne 0x00 always reads back 0x00 0x5f jesd 204b l ink control 1 serial tail bit enable : 0 = extra bits are 0 , 1 = extra bits are 9 - bit pn jesd204b test sample enable reserved; s et to 1 ilas m ode : 01 = ilas normal mode enabled , 11 = ilas always on, test m ode reserved; set to 1 jesd204b l ink power - down ; s et high while configuring l ink parameters 0x14 0x60 jesd 204b l ink control 2 reserved; set to 0 reserved; set to 0 reserved; set to 0 syncinb logic t ype : 0 = lvds (differential) , 1 = cmos (single - ended) reserved; set to 0 invert transmit bits reserved; set to 0 0x00 0x61 jesd 204b l ink ctrl 3 reserved; set to 0 reserved; set to 0 test data injection point : 01 = 10- bit data at 8b/10b output , 10 = 8 - bit data at scrambler input jesd204b test mode patter ns: 0000 = normal operation (test mode disabled) , 0001 = alternating checker board , 0010 = 1/0 word toggle , 0011 = pn sequence pn23 , 0100 = pn sequence pn9 , 0101 = continuous/repeat user test mode , 0110 = single user test mode , 0111 = r eserved , 1100 = pn sequence pn7 , 1101 = pn sequence pn15 , o ther setting are unused 0x00 0x64 jesd 204b did config jesd204b did value
ad9683 data sheet rev. 0 | page 38 of 44 reg addr (hex) reg addr name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) defaul t notes 0x65 jesd 204b bid config jesd204b bid value 0x67 jesd 204b lid c onfig jesd204b lid value 0x6e jesd 204b scrambler (s cr) and lane (l) configuration jesd204b scrambling (scr) : 0 = disabled , 1 = enabled jesd204b number of lanes (l) ; 0 = o ne lane per link (l = 1) 0x80 0x6f jesd 204b p arameter , f jesd204b number of octets per frame (f) ; c alculated value ; read only read o nly 0x70 jesd 204b p arameter , k jesd204b number of frames per multiframe (k) ; set value of k per jesd204b spec ifications , but must also be a multiple of four octets 0x71 jesd 204b p arameter , m jesd204b number of converters (m) ; 0 = 1 c onverter 0x00 re ad o nly 0x72 jesd 204b p arameters , n / cs number of c ontrol bits (cs) : 00 = n o control bits (cs = 0) , 01 = 1 c ontrol bit (cs = 1) , 10 = 2 c ontrol bits (cs = 2) adc converter resolution (n) , 0xd = 14- bit c onverter (n = 14) 0x0d 0x73 jesd 204b p arame ters , s ub c lass/n jesd204b s ubclass : 00 = subclass 0 , 01 = subclass 1 ( d efault) jesd204b n value ; 0xf = n = 16 0x2f 0x74 jesd 204b p arameter , s reserved; set to 1 jesd204b s amples per converter per frame cycle (s) ; r ead only 0x75 jesd 204b p aram eters , hd and cf jesd204b hd value ; read only jesd204b control word s per frame clock cycle per link (cf) ; r ead o nly read o nly 0x76 jesd 204b resv1 jesd204b r eserved field 1 0x77 jesd 204b resv2 jesd204b r eserved field 2 0x79 jesd 204b chksum jesd204 b checksum value for the output lane 0x80 jesd 204b output driver control jesd204b driver power - d own : 0 = e nabled , 1 = powered down 0x00 0x8b jesd 204b lmfc o ffset local multiframe clock (lmfc) phase offset value; r eset value for lmfc p hase co unter when sysref is asserted ; u sed for deterministic delay applications 0x00 0xa 8 jesd 204b p reemphasis jesd204b p reemphasis enable option ( c onsult factory for more detail s ) ; s et value to 0x04 for p reemphasis off , and s et value to 0x14 for p r e emphasis on 0x04 typically not required 0xff device update ( global ) transfer s ettings memory map register description s for more informat ion on functions controlled in address 0x00 to address 0x 2 1 and address 0xff , with the exception of address 0x08 and address 0x14, see the an - 877 application note , interfacing to high speed adcs via spi . pdwn modes (address 0x08) bits76 reserved bit 5 external pdwn mode this bit controls the function of th e pdwn pin. when this bit is 0, asserting the p dwn pin results in a full power - down of the device. when this bit is 1, asserting the pdwn pin places the device in standby.
data sheet ad9683 rev. 0 | page 39 of 44 bit 4 jesd204b standby m ode this bit controls the state of the jesd204b digital cir cuitry when the external pdwn pin is used to place the device into standby. if this bit is 0, the jes204b digital circuitry is not placed into standby. when this bit is 1, the jesd204b circuitry is placed into standby when the pdwn pin is asserted and bit 5 is 1. bit s [3:2] jesd204b power modes these bits control the power modes of the jesd204b digital circuitry. when b its[3:2] = 00 , the jesd204b digital circuitry is in normal mode. when b its[3:2] = 01 , the jesd204 b digital circuitry is in power - down mode wi th the pll off, serializer off, clocks stopped, and the digital circuitry held in reset. when b its[3:2] = 10 the jesd204b digital circuitry is placed into standby mode with the pll on, serial izer off, clocks stopped, and the digital circuitry held in reset . bits[1:0] adc power m odes these bits select power mode for the adc excluding the jesd204b digital circuitry. when bits[1:0] = 00, the adc is in normal mode. when bits[1:0] = 01, the adc is placed into power - down mode, and when bits[1:0] = 10, the adc is placed into standby mode. output mode (address 0x 14) bit s[ 7 :5] jesd204b cs bits assignment these bits control the function of the cs bits in the jesd204b serial data stream. bit 4 adc output disable if this bit is set, the output data from the adc is di sabled. bit 3 open bit 2 adc data invert if this bit is set, the output data from the adc is inverted. bits[ 1 : 0 ] data format select these bits select the output data format. when b its[1:0] = 00, the output data is in offset binary format , and when b its[ 1:0] = 01, the output data is in twos complement format. syncinb /sysref control ( address 0x3a) bits[7:5] reserved bit 4 jesd204b r ealign syncinb when this bit is set low, the jesd204b link operates in normal mode. when this bit is high, the jesd204b lin k realigns on every active syncinb assertion. bit 3 jesd204b r ealign sysref when this bit is set low, the jesd204b link operates in normal mode. when this bit is high, the jesd204b link realigns on every active sysref assertion. bit 2 sysref m ode when this bit is set low, the clock dividers are continuously reset on each sysref assertion. when this bit is high, the clock dividers are reset on the next rising edge of sysref only. bit 1 sysref e nable when this bit is set low, the sysref input is disab led. when this bit is high, the sysref input is enabled. bit 0 enable syncinb b uffer when this bit is set low, the syncinb input buffer is disabled. when this bit is high, the syncinb input buffer is enabled. dc correction control ( address 0x40) bit 7 reserved bit 6 freeze dc correction when bit 6 is set low, the dc correction is continuously calculated . when bit 6 is set high, the dc correction is no longer updated to the signal monitor block, which holds the last dc value calculated. bits[5:2] dc cor rection bandwidth select bits[5:2] set the averaging time of the signal monitor dc correction function. this 4 - bit word sets the bandwidth of the correction block, according to the following equation: = ? ? 2 2 _ _ 14 clk k f bw corr dc where: k is the 4 - bit value pr ogrammed in bits[5:2] of address 0x40 (values between 0 and 13 are valid for k; programming 14 or 15 provides the same result as programming 13). f clk is the ad9683 adc sample rate in hertz. bit 1 enable dc correction setting this bit high causes the outp ut of the dc measurement block to be summed with the data in the signal path to remove the dc offset from the signal path. bit 0 reserved dc correction value 0 ( address 0x41) bits[7:0] dc correction value lsb [7:0] these bits are the lsbs of the dc correcti on value. dc correction value 1 ( address 0x42) bits[7:0] dc correction v alue msb [15:8] these bits are the msbs of the dc correction value. fast detect control ( address 0x45) bits[7: 5 ] reserved bit 4 fd pin function when this bit is set low, the fd pin fun ctions as the fast detect output. when this pin is set high , the fd pin functions as the overrange indicator. bit 3 force fd output enable setting this bit high forces the fd output pin to the value written to bit 2 of this register ( address 0x45). this enables the user to force a known value on the fd pin for debugging. bit 2 force d fd output value the value written to bit 2 is forced on the fd output pin when bit 3 is written high.
ad9683 data sheet rev. 0 | page 40 of 44 bit 1 reserved bit 0 enable fast detect output setting this bit high enables the output of the upper threshold fd comparator to drive the fd output pin. fast detect upper threshold ( address 0x47 and address 0x48) address 0x48, bit 7 reserved address 0x48, bits[ 6 :0] fast detect upper threshold [1 4 :8] address 0x47, bits[7:0] fast detect upper threshold [7:0] these registers provide an upper limit threshold. the 1 5 - bit value is compared with the output magnitude from the adc block. if the adc magnitude exceeds this threshold value, the fd output pin is set when bit 0 in address 0x45 is set. fast detect lower threshold ( address 0x49 and address 0x4a) address 0x4a, bit 7 reserved address 0x4a, bits[ 6 :0] fast detect lower threshold [1 4 :8] address 0x49, bits[7:0] fast detect lower threshold [7:0] these registers prov ide a lower limit threshold. the 1 5 - bit value is compared with the output magnitude from the adc block. if the adc magnitude is less than this threshold value for the number of cycles programmed in the fast detect dwell time register, the fd output bit is cleared. fast detect dwell time ( address 0x4b and address 0x4c) address 0x4c, bits[7:0] fast detect dwell time[15:8] address 0x4b, bits[7:0] fast detect dwell time[7:0] these register values set the minimum time in adc sample clock cycles (after clock div ider) that a signal needs to stay below the lower threshold limit before the fd output bits are cleared. jesd204b quick configuration (address 0x5e) bits[7:0] jesd204b quick configuration these bits serve to quickly set up the default jesd204b link paramet ers for m = 1 and l = 1. jesd204b link control 1 (address 0x5f) bit 7 open bit 6 serial tail bit enable if this bit is set and the cs bits are not enabled , unused tai l bits are padded with a pseudo random number sequence from a 9 - bit lfsr (see jesd204b 5.1 .4). bit 5 jesd204b test sample enable if set, jesd204b test samples are enabled, and the long transport layer test sample sequence (as specified in jesd204b section 5.1.6. 3 ) sent on all link lanes. bit 4 reserved ; s et to 1 bits[3:2] ilas m ode 01 = initial lane alignment sequence enabled. 11 = initial lane alignment sequence always on in test mode; jesd204b data link layer test mode where the repeated lane alignment sequence (as specified in jesd204b 5.3.3.8.2) is sent on all lanes. bit 1 reserved ; s et to 1 bit 0 jesd204b link power - down if bit 0 is set high, the serial transmit link is held in reset with its clock gated off. the jesd204b transmitter must be powered down when changing any of the link configuration bits. jesd204b link control 2 (addr ess 0x6 0 ) bits[7: 5 ] reserved ; s et to 0 bit 4 syncinb logic t ype 0 = lvds differential pair syncinb input (default). 1 = cmos single - ended syncinb using the syncinb ? input. bit 3 open bit 2 reserved ; s et to 0 bit 1 invert transmit bi ts setting this bit inverts the 10 serial output bits. this effectively inverts the output signals. bit 0 reserved ; s et to 0 jesd204b link control 3 (address 0x6 1 ) bit [ 7 :6] reserved ; s et to 0 bits[5:4] te st data injection point 01 = 10- bit test generation data injected at output of 8b / 10b encoder (at input to phy). 10 = 8 - bit test generation data injected at input of scrambler bits[ 3 :0] jesd204b test mode patterns 000 0 = normal operat ion (test mode disabled). 0 001 = alternating checkerboard. 0 010 = 1/0 word toggle. 0 011 = pn 23 sequence . 0 100 = pn 9 sequence. 0 101 = continuous/repeat user test mode. the most significant bits from the user pattern (1, 2, 3, 4) are placed on the output for one clock cycle and then the output user pattern is repeated (1, 2, 3, 4, 1, 2, 3, 4, 1, 2, 3, 4.) . 0 110 = single user test mode. the most significant bits from the user pattern (1, 2, 3, 4) are placed on the output for one clock cycle, and then all zero s are output ( output user pattern 1, 2, 3, 4 ; then output all zeros) . 0111 = reserved. 1100 = pn7 sequence. 1101 = pn15 sequence. others = unus ed.
data sheet ad9683 rev. 0 | page 41 of 44 jesd204b device identification (did) configuration (address 0x6 4 ) bits[7:0] jesd204b device identification ( did) v alue jesd204b bank identification (bid) configuration (address 0x65) bits[7:4] open bits[3:0] jesd204b bank identification (bid) v alue jesd204b lane identification (lid) configuration (address 0x67) bits[7:5] open bits[4:0] jesd204b lane identificati on ( l id) v alue jesd204b scrambler (scr) and lane (l) configuration (address 0x6e) bit 7 jesd204b s crambling (scr ) when this bit is set to low, it disables the scrambler (scr = 0). when this bit is set to high, it enables the scrambler (scr = 1). bits[6: 5 ] open bits[4:0] jesd204b number of lanes (l) 0 = one lane per link (l = 1). jesd204b parameter , f (address 0x6f, read only) bits[7:0] jesd204b number of octets per frame (f) the readback from this register is calculated from the following equation: f = (m 2)/l. the v alid value for f is f = 2, with m = 1 and l = 1 . jesd204b parameter , k (address 0x70) bits[ 7 :0] jesd204b number of frames per multiframe (k) this register sets the k value for the jesd204b interface which defines the number of frames pe r multiframe. the value must be a multiple of 4. jesd204b parameter , m (address 0x71) bit s [7: 0 ] j esd204b number of converters (m) 0 = link connected to one adc. only primary input used (m = 1 ). jesd204b parameters , n/cs (address 0x72) bits[7:6] number of control bi ts (cs) 00 = no control bits sent per sample (cs = 0). 01 = one control bit sent per sample overrange bit enabled (cs = 1). 10 = two control bits sent per sample overflow/underflow bits enabled (cs = 2). bit s [ 5 :4] open bits [ 3 :0] adc convert er resolution (n) read only bits showing the converter resolution (reads back 13 (0xd) for 14 - bit resolution). jesd204b parameter , subclass/n ( address 0x73) bit 7 reserved bits[6:5] jesd204b s ubclass when bits[6:5] are 00 , the device operates in s ubcl ass 0 mode , and when bits[6:5] are 01 , the device operates in s ubclass 1 mode. bit 4 reserved bits[ 3 :0] jesd204b n v alue read only bits showing the total number of bits per sample, minus 1 (reads back 15 (0xf) for 16 bits per sample). jesd204b samples p er converter per frame cycle (s) ( address 0x74) bits[7: 6 ] open bit 5 reserved ; s et to 1 bits[4:0] jesd204b samples per converter per frame per cy cle (s) read only bits showing the number of samples per converter frame cycle, minus 1 (reads back 0 (0x0) fo r one sample per converter frame). jesd204b parameters hd and cf ( address 0x75) bit 7 jesd204b high density (hd) value (read only ) read only bit. always set to 0. bits[6:5] open bits[4:0] jesd204b control words per frame clock cycle per link (cf) read onl y bits. reads back 0x0. jesd204b reserved 1 ( address 0x76) bits[7:0] jesd204b reserved field 1 this read/write register is available for customer use. jesd204b reserved 2 ( address 0x77) bits[7:0] jesd204b reserved field 2 this read/write register is avai lable for customer use. jesd204b checksum (address 0x7 9 ) bits[7:0] jesd204b checksum value for the output lane this read only register is automatically calculated for the lane. checksum equals s um (all link configuration parameters for the lane) modulus 2 56. jesd204b output driver control (address 0x80) bits[7:1] reserved bit 1 jesd204b driver power - down when this bit is set low, the jesd204b output drivers are enabled . when this bit is set high, the jesd204b output drivers are powered down.
ad9683 data sheet rev. 0 | page 42 of 44 jesd204b lmfc offset (address 0x8b) bits[7:5] reserved bits[4:0] local multiframe clock phase offset value these bits are the reset value for the local multiframe clock (lmfc) phase counter when sysref is asserted. these bits are used in applications requiring d eterministic delay. jesd204b pre e mphasis (address 0xa8) bits[7:0] jesd204b preemphasis enable option these bits enable the preemphasis feature on the jesd204b output drivers. setting bits[7:0] to 0x04 disables premphasis , and setting bits[7:0] to 0x14 e nables preemphasis.
data sheet ad9683 rev. 0 | page 43 of 44 applications information design guidelines before starting system level de sign and layout of the ad9683 , it is recommended that the designer become familiar with these gu idelines, which describe the special circuit connections and layout requirements needed for certain pins. power and ground recommendations when connecting power to the ad9683 , it is recommended tha t two separate 1.8 v power supplies be used . t he power supply for avdd can be isolated , and the power supply for dvdd and drvdd can be tied together , in which case , an isolation inductor of approximately 1 h is recommended. alternat iv ly, the jesd204b phy power (drvdd) and analog (avdd) supplies can be tied together , and a separate supply can be used for the digital outputs (dvdd). the designer can employ several different decoupling capacitors to cover both high and low frequencies. place t hese capacitors close to the point of entry at the pc b level and close to the pins of the part with minimal trace length. when using the ad9683 , a single pcb ground plane is sufficient. with proper decoupling and smart partitioning of the pcb analog, digital, and clock sections, optimum performance is easily achieved. exposed pad thermal heat slug recommendations it is mandatory that the exposed pad on the underside of the adc be connected to analog ground (agnd) to achieve the best electrical and thermal performance. mate a continuous, exposed (no solder mask) copper plane on the pcb to the ad9683 exposed pad. the copper plane should have several vias to achieve the lowest possible resistive thermal path for heat dissipation to flow through the bottom of the pcb. fill or plug t hese with nonconductive epoxy. to maximize the coverage and adhesion between the adc and the pcb, overlay a silkscreen to partition the continuous plane on the pcb into several uniform sections. this provides several tie points between the adc and the pcb during the reflow process. using one continuous plane with no partitions guarantees only one tie point between the adc and the pcb. see the evaluation board for a pcb layout example. for detailed information about the packaging and pcb layout of chip scale packages, refer to the an - 772 application note , a design and manufactur ing guide for the lead frame chip scale package (lfcsp) . vcm decouple t he vcm pin to ground with 0.1 f capacitor s , as shown in figure 45. it is recommended to place one 0.1 f capacitor as close as possible to the vcm pin and another at the vcm connection to the analog input network. spi port do not activate t he spi port during periods when the full dynamic performance of the converter is required. because the sclk, cs , and sdio signals are typica lly asynchronous to the adc clock, noise from these signals can degrade converter performance . if the on - board spi bus is used for other devices, it may be necessary to provide buffers between this bus and the ad9683 to keep these signals from transitioning at the converter input pins during critical sampling periods.
ad9683 data sheet rev. 0 | page 44 of 44 outline dimensions 0 8 - 1 6 - 2 0 1 0 - b 1 0 . 5 0 b s c b o t t o m v i e w t o p v i e w p i n 1 i n d i c a t o r 3 2 9 1 6 1 7 2 4 2 5 8 e x p o s e d p a d pin 1 indica t or s e a t i n g p l a n e 0 . 0 5 m a x 0 . 0 2 n o m 0 . 2 0 r e f c o p l a n a r i t y 0 . 0 8 0 . 3 0 0 . 2 5 0 . 1 8 5 . 1 0 5 . 0 0 s q 4 . 9 0 0 . 8 0 0 . 7 5 0 . 7 0 f o r p r o p e r c o n n e c t i o n o f t h e e x p o s e d p a d , r e f e r t o t h e p i n c o n f i g u r a t i o n a n d f u n c t i o n d e s c r i p t i o n s s e c t i o n o f t h i s d a t a s h e e t . 0 . 5 0 0 . 4 0 0 . 3 0 0 . 2 5 m i n * 3 . 7 5 3 . 6 0 s q 3 . 5 5 * c o m p l i a n t t o j e d e c s t a n d a r d s m o - 2 2 0 - w h h d - 5 w i t h e x c e p t i o n t o e x p o s e d p a d d i m e n s i o n . figure 68 . 32 - lead lead frame chip scale package [lfcsp_ w q] 5 mm 5 mm body, very very thin quad (cp - 32 - 12 ) dimensions shown in millimeters ordering guide model 1 temperature range package description package option ad9683 bcpz -170 ?40c to +85c 32- lead lead frame chip scale package [lfcsp_ w q] cp -32-12 ad9683 bcpz rl7 - 170 ?40c to +85c 32- lead lead frame chip scale package [lfcsp_ w q] cp -32-12 ad9683 - 170ebz ?40c to +85c evaluation board with ad9683 - 170 ad9683 bcpz -250 ?40c to +85c 32- lead lead frame chip scale package [lfcsp_ w q] cp -32-12 ad9683 bcpzrl7 - 250 ?40c to +85c 32- lead lead frame chip scale package [lfcsp_ w q] cp -32-12 ad9683 - 250ebz ?40c to +85c evaluation board with ad9683 - 250 1 z = rohs compliant part. ? 2013 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d11410 - 0 - 4/13(0)

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